Sigma-delta configurations for capacitance sensing

Patent metadata

Field	Value
Publication number	US-10816582-B2
Application number	US-201816178827-A
Country	US
Kind code	B2
Filing date	Nov 2, 2018
Priority date	Nov 2, 2018
Publication date	Oct 27, 2020
Grant date	Oct 27, 2020

Abstract

An input device includes a clocked comparator configured to actively drive a capacitive sensor electrode at a signal input of the clocked comparator with a first periodic reference voltage, and provide a digital representation of a sensing current resulting from driving the capacitive sensor electrode with the first periodic reference signal. The clocked comparator produces the digital representation of the sensing current based on a comparison of the signal input of the clocked generator with the first periodic reference signal. A feedback path provides negative feedback of the digital representation of the sensing current to the signal input of the clocked comparator. The input device further includes a demodulator configured to demodulate the digital representation of the sensing current using the first periodic reference signal to obtain a first digital measurement.

First claim

What is claimed is:

1. An input device, comprising:
a clocked comparator configured to:
actively drive a capacitive sensor electrode at a signal input of the clocked comparator with a first periodic reference signal; and
provide a digital representation of a sensing current resulting from driving the capacitive sensor electrode with the first periodic reference signal,
wherein the clocked comparator produces the digital representation of the sensing current based on a comparison of the signal input of the clocked comparator with the first periodic reference signal, and
wherein a feedback path provides negative feedback of the digital representation of the sensing current to the signal input of the clocked comparator; and

a demodulator configured to demodulate the digital representation of the sensing current using the first periodic reference signal to obtain a first digital measurement.

2. The input device of claim 1 , wherein a clock frequency of the clocked comparator is selected to oversample the signal input of the clocked comparator.

3. The input device of claim 1 , further comprising:
a demodulator, a low pass filter, and a decimator configured to down sample the first digital measurement.

4. The input device of claim 3 , wherein the demodulator, the low pass filter, and the decimator are implemented as a coefficient generator and a multiplier-accumulator.

5. The input device of claim 1 , further comprising:
a direct digital synthesizer configured to generate the first periodic reference signal.

6. The input device of claim 1 , wherein the first digital measurement comprises a quadrature signal.

7. The input device of claim 1 , further comprising:
a second demodulator configured to demodulate the digital representation of the sensing current using a second periodic reference signal to obtain a second digital measurement.

8. The input device of claim 7 , wherein the first and the second periodic reference signals are different frequencies.

9. The input device of claim 8 ,
wherein the second periodic reference signal is used to drive an electrode in proximity to the capacitive sensor electrode, and
wherein the second digital measurement reflects a transcapacitance between the capacitive sensor electrode and the electrode in proximity of the capacitive sensor electrode.

10. The input device of claim 8 , wherein the second digital measurement is associated with a signal of an active stylus in proximity to the capacitive sensor electrode.

11. The input device of claim 1 ,
wherein the clocked comparator is a multi-bit analog-to-digital (A/D) converter, and
wherein the A/D converter produces the digital representation of the sensing current based on the comparison of the input of the A/D converter with at least a second periodic reference signal, in addition to the first periodic reference signal.

12. An input device, comprising:
a first active integrator and an analog-to-digital (A/D) converter in series and configured to:
actively drive a capacitive sensor electrode at a signal input of the active integrator with a periodic reference signal; and
provide, at an output of the A/D converter, a digital representation of a sensing current resulting from driving the capacitive sensor electrode with the periodic reference signal,
wherein the periodic reference signal is provided to a reference input of the first active integrator, and
wherein a feedback path provides negative feedback of the digital representation of the sensing current to the signal input of the active integrator; and

a demodulator configured to demodulate the digital representation of the sensing current using the periodic reference signal to obtain a digital measurement.

13. The input device of claim 12 , wherein the periodic reference signal is further provided as a reference to the A/D converter.

14. The input device of claim 12 , further comprising:
a second active integrator between the first active integrator and the A/D converter.

15. A method for operating an input device, comprising:
obtaining a periodic reference signal;
actively driving a capacitive sensor electrode at a signal input of a clocked comparator with the periodic reference signal;
producing, by the clocked comparator, a digital representation of a sensing current based on a comparison of the signal input of the clocked comparator with the periodic reference signal;
providing negative feedback of the digital representation of the sensing current to the signal input of the clocked comparator by a feedback path; and
demodulating the digital representation of the sensing current using the periodic reference signal to obtain a digital measurement.

16. The method of claim 15 , further comprising downsampling the digital measurement.

17. The method of claim 15 ,
wherein the clocked comparator is a component of a sigma-delta circuit, and
wherein the periodic reference signal is a reference input to the sigma-delta circuit.

18. The method of claim 15 , wherein the clocked comparator is an analog to digital converter.

19. The method of claim 15 , wherein the digital measurement reflects an absolute capacitance of the capacitive sensor electrode.

20. The method of claim 15 , wherein the digital measurement comprises a quadrature signal.

Assignees

• Synaptics Inc

Inventors

• Hargreaves Kirk

Classifications

• H03K17/955

  using a capacitive detector · CPC title

• H03K17/962

  Capacitive touch switches · CPC title

• G06F3/044

  by capacitive means · CPC title

• G06F3/04182

  Filtering of noise external to the device and not generated by digitiser components · CPC title

• H03M3/454

  with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage · CPC title