Techniques for computing dot products with memory devices

Patent metadata

Field	Value
Publication number	US-10812083-B2
Application number	US-201916669324-A
Country	US
Kind code	B2
Filing date	Oct 30, 2019
Priority date	Apr 24, 2017
Publication date	Oct 20, 2020
Grant date	Oct 20, 2020

Abstract

Sparse representation of information performs powerful feature extraction on high-dimensional data and is of interest for applications in signal processing, machine vision, object recognition, and neurobiology. Sparse coding is a mechanism by which biological neural systems can efficiently process complex sensory data while consuming very little power. Sparse coding algorithms in a bio-inspired approach can be implemented in a crossbar array of memristors (resistive memory devices). This network enables efficient implementation of pattern matching and lateral neuron inhibition, allowing input data to be sparsely encoded using neuron activities and stored dictionary elements. The reconstructed input can be obtained by performing a backward pass through the same crossbar matrix using the neuron activity vector as input. Different dictionary sets can be trained and stored in the same system, depending on the nature of the input signals. Using the sparse coding algorithm, natural image processing is performed based on a learned dictionary.

First claim

What is claimed is:

1. A memory device comprising:
an array of memory cells arranged in columns and rows;
an interface circuit, coupled to the array of memory cells, and configured to;
receive a set of first vectors and a second vector;
load the set of first vectors in the array of memory cells;
compute a third vector as a dot product of the second vector and the set of first vectors by feeding the second vector forward through the array of memory cells loaded with the first vector;
compute a fourth vector as a non-linear transform of the third vector;
compute a fifth vector as a dot product of the fourth vector and a transpose of the set of first vectors by feeding the fourth vector backward through the array of memory cells loaded with the set of first vectors;
compute a sixth vector as a difference between the fifth vector and the second vector; and
compute a new instance of the third vector as a dot product of the sixth vector and the first vector by feeding the sixth vector through the array of memory cells loaded with the first vector.

2. The memory device of claim 1 , wherein the interface circuit configured to load the set of first vectors comprises:
the interface circuit further configured to set one or more memory cell parameters of the array to memory cells to correspond to element values in the set of first vectors.

3. The memory device of claim 1 , wherein the interface configured to compute the third vector as a dot product of the second vector and the set of first vectors comprises:
the interface circuit further configured to apply drive signals to corresponding rows of the array of memory cells, wherein the drive signals have one or more fixed signal parameters corresponding to element values of the second vector; and
the interface circuitry further configured to sense signals from corresponding columns of the array of memory cells, wherein the sense signals have one or more signal parameters representing element values of the third vector.

4. The memory device of claim 3 , wherein the interface configured to compute the fifth vector as a dot product of the fourth vector and the transpose of the set of first vectors comprises:
the interface circuit further configured to apply drive signals to corresponding columns of the array of memory cells, wherein the drive signals have one or more fixed signal parameters corresponding to element values of the fourth vector; and
the interface circuitry further configured to sense signals from corresponding rows of the array of memory cells, wherein the sense signals have one or more signal parameters representing element values of the filth vector.

5. The memory device of claim 1 , wherein the interface circuit configured to compute a fourth vector as a non-linear transform of the third vector comprises:
the interface circuit further configured to evaluate elements of the third vector in relation to a threshold, including to set a value of elements of the fourth vector to zero when a corresponding value of an element in the third vector is less than the threshold and to set the value of elements of the fourth vector to the corresponding value of the element in the third vector when the corresponding value of the element in the third vector is greater than the threshold.

6. The memory device of claim 1 , wherein the third vector represents a sparse coding of the first vector.

7. The memory device of claim 1 , wherein the array of memory cells comprise a crossbar array of memristor cells.

8. The memory device of claim 1 , wherein the array of memory cells comprise a crossbar array of phase change cells.

9. The memory device of claim 1 , wherein:
the array of memory cells are disposed in a first layer of an integrated circuit; and
the interface circuit is disposed in a second layer of the integrated circuit and is coupled to the array of memory cells by interlayer vias (ILV).

10. The memory device of claim 1 , wherein the interface circuit is further configured to:
compute a new instance of the fourth vector as the non-linear transform of the new instance of the third vector,
compute a new instance of the fifth vector as the dot product of the new instance of the fourth vector and the transpose of the set of first vectors by feeding the new instance of the fourth vector backward through the array of memory cells loaded with the set of first vectors;
compute a new instance of the sixth vector as a difference between the new instance of the fifth vector and the second vector; and
compute a new instance of the third vector as the dot product of the new instance of the sixth vector and the set of first vectors by feeding the new instance of the third vector through the array of memory cells loaded with the set of first vectors.

11. The memory device of claim 10 , wherein the interface circuit is further configured to iteratively compute the new instance of the fourth vector, the new instance of the fifth vector, the new instance of the sixth vector, and the new instance of the third vector a predetermined number of times.

12. A memory device comprising:
an array of memory cells arranged in columns and rows, wherein the array of memory cells include a plurality of tiles of the memory cells;
a number of interface circuits coupled to the plurality of tiles of the array of memory cells, and wherein a first one of the number of interface circuits is configured to;
load a set of one or more first vectors in a first one of the plurality of tiles of the array of memory cells;
feed a second vector forward through the first tile of the array of memory cells to compute a third vector as a dot product of the set of one or more first vectors and the second vector, and
feed a fourth vector backward through the first tile of the array of memory cells to compute a fifth vector as a dot product of the fourth vector and a transpose of the set of one or more first vectors.

13. The memory device of claim 12 , wherein the first interface circuit is further configured to:
compute the fourth vector based on the third vector.

14. The memory device of claim 13 , wherein the first interface circuit is further configured to:
compute a sixth vector as a difference between the fifth vector and the second vector.

15. The memory device of claim 14 , wherein the first interface circuit is further configured to:
feed the sixth vector forward through the first tile of the array of memory cells to compute a new instance of the third vector as a dot product of the sixth vector and the set of one or more first vectors.

16. The memory device of claim 12 wherein a second one of the interface circuits is configured to:
load a set of one or more seventh vectors in a second one of the plurality of tiles of the array of memory cells;
feed an eighth vector forward through the second tile of the array of memory cells to compute a ninth vector as a dot product of the eighth vector and the set of one or more seventh vectors; and
feed a tenth vector backward through the second tile of the array of memory cells to compute an eleventh vector as a dot product of the tenth vector and a transpose of the set of one or more seventh vectors.

17. The memory device of claim 16 , wherein the first and second interface circuits are configured to:
feed the second vector forward through the first tile of the array of memory cells to compute the third vector as the dot product of the second vector and the set of one or more first vectors, and feed the eighth vector forward through the second tile of the array of memory cells to compute the nin

Assignees

• Univ Michigan Regents

Inventors

• Lu Wei
• Cai Fuxi
• Sheridan Patrick
• Du Chao

Classifications

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• H04L49/101

  using crossbar or matrix · CPC title

• G11C2213/77

  Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used · CPC title

• H03K19/17748 Primary

  Structural details of configuration resources · CPC title

• H04Q11/00

  Selecting arrangements for multiplex systems (multiplex systems H04J) · CPC title