Multi-stage charge pump with inter-stage limitation circuit

Patent metadata

Field	Value
Publication number	US-10811963-B2
Application number	US-201816172381-A
Country	US
Kind code	B2
Filing date	Oct 26, 2018
Priority date	Oct 26, 2018
Publication date	Oct 20, 2020
Grant date	Oct 20, 2020

Abstract

A multi-stage charge pump circuit including a first stage of the multi-stage charge pump having a first voltage output, a last stage of the multi-stage charge pump having a first voltage input, and an inter-stage limitation circuit configured to protect a voltage drop of the first voltage output of the first stage of the multi-stage charge pump when there is a voltage drop on the first voltage input of the last stage of the multi-stage charge pump.

First claim

The invention claimed is:

1. A multi-stage charge pump circuit, comprising:
a first stage of the multi-stage charge pump having a first voltage output;
a last stage of the multi-stage charge pump having a first voltage input; and
an inter-stage limitation circuit configured to protect a voltage drop of the first voltage output of the first stage of the multi-stage charge pump when there is a voltage drop on the first voltage input of the last stage of the multi-stage charge pump.

2. The multi-stage charge pump circuit of claim 1 , wherein the first voltage output of the first stage of the multi-stage charge pump connects to the first voltage input of the last stage of the multi-stage charge pump through the inter-stage limitation circuit.

3. The multi-stage charge pump circuit of claim 1 , wherein the inter-stage limitation circuit includes a PMOS transistor in parallel with a large size resistor.

4. The multi-stage charge pump circuit of claim 3 , wherein the PMOS transistor is configured to be ON during a steady state action of the multi-stage charge pump.

5. The multi-stage charge pump circuit of claim 3 , wherein the PMOS transistor is configured to be OFF when the first voltage input drops from a high state to a low state.

6. The multi-stage charge pump circuit of claim 1 , wherein the inter-stage limitation circuit includes a first storage capacitor associated with the first voltage output.

7. The multi-stage charge pump circuit of claim 1 , wherein the inter-stage limitation circuit includes a second storage capacitor associated with the first voltage input.

8. The multi-stage charge pump circuit of claim 1 , wherein the first voltage output is configured to provide power to other circuits external to the multi-stage charge pump.

9. The multi-stage charge pump circuit of claim 1 , wherein the inter-stage limitation circuit includes a small size resistor in series with a large size resistor.

10. The multi-stage charge pump circuit of claim 9 , comprising an intermediary capacitor disposed between the small size resistor and the large size resistor.

11. A method of operating a multi-stage charge pump, comprising:
ramping up a first voltage output of a first-stage charge pump;
ramping up a second voltage output of a last-stage charge pump in order to supply a voltage of an external switch;
limiting a current draw on the first voltage output by enabling a high resistance between the first voltage output of the first-stage charge pump and a first voltage input of the last-stage charge pump.

12. The method of claim 11 , comprising switching off a PMOS transistor that is in parallel with the high resistance to enable the high resistance between the first stage and the last stage.

13. The method of claim 11 , comprising switching on a PMOS transistor that is in parallel with the high resistance to disable the high resistance between the first stage and the last stage.

14. The method of claim 11 , wherein the first voltage output is configured to provide power to other circuits.

15. The method of claim 11 , comprising storing a first charge in a first capacitor adjacent an output of the first stage.

16. The method of claim 11 , comprising storing a second charge in an intermediate capacitor between the first stage and the last stage.

17. The method of claim 11 , comprising storing a second charge in a second capacitor adjacent an input of the last stage.

18. The method of claim 11 , comprising storing and ramping up charge using a plurality of capacitors arranged in parallel.

Assignees

• Nxp Bv

Inventors

• Liu Xiaoqun
• Vemula Madan Mohan Reddy

Classifications

• H02M3/075

  including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages · CPC title

• H02M1/0045

  Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode · CPC title

• H02M1/08

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H02M1/32 Primary

  Means for protecting converters other than automatic disconnection · CPC title

• H02H9/025

  Current limitation using field effect transistors · CPC title