Voltage multiplier circuit with a common bulk and configured for positive and negative voltage generation

Patent metadata

Field	Value
Publication number	US-10811960-B2
Application number	US-201916563069-A
Country	US
Kind code	B2
Filing date	Sep 6, 2019
Priority date	Oct 23, 2017
Publication date	Oct 20, 2020
Grant date	Oct 20, 2020

Abstract

A voltage doubler circuit supports operation in both a positive voltage boosting mode to positively boost voltage from a first node to a second node and a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuit is formed by transistors of a same conductivity type that share a common bulk that is not tied to a source of any of the voltage doubler circuit transistors. A bias generator circuit is coupled to receive a first voltage from the first node and second voltage from the second node. The bias generator circuit operates to apply a lower one of the first and second voltages to the common bulk.

First claim

What is claimed is:

1. A circuit, comprising:
a voltage multiplier circuit including:
first and second intermediate nodes that are capacitively coupled to receive opposite phases of a first clock signal, respectively; and
a first transistor and a second transistor connected in a cross-coupled configuration, wherein a first conduction terminal of the first transistor and a gate terminal of the second transistor are connected to the first intermediate node and wherein a first conduction terminal of the second transistor and a gate terminal of the first transistor are connected to the second intermediate node;
wherein said first and second transistors have a same conductivity type and share a common bulk that is not tied to a source of either of said first and second transistors; and

a bias generator circuit configured to apply a bias voltage to the common bulk of the first and second transistors.

2. The circuit of claim 1 , wherein the bias generator circuit receives a first voltage from a first node and a second voltage from a second node, said bias generator circuit configured to apply a lower one of the first and second voltages to the common bulk.

3. The circuit of claim 2 , wherein each of the first and second transistors has a source-drain path coupled between the first node and the second node.

4. The circuit of claim 3 , wherein sources of the first transistor and second transistor are connected to the first node.

5. The circuit of claim 2 , wherein said bias generator circuit comprises: a first biasing transistor and a second biasing transistor having source-drain paths coupled in series between the first and second nodes at a common source that is connected to said common bulk and wherein gates of the first and second biasing transistors are cross-coupled to drains of the second and first biasing transistors, respectively.

6. The circuit of claim 5 , wherein the first and second biasing transistors have the same conductivity type as the first and second transistors of the voltage multiplier circuit.

7. The circuit of claim 6 , wherein the first and second biasing transistors have sources and drains formed in the common bulk and wherein the first and second transistors of the voltage multiplier circuit have sources and drains formed in the common bulk.

8. The circuit of claim 1 , wherein said first and second transistors are implemented in a triple well technology including a p-type region, an isolated n-type well in the p-type region and a p-type well forming said common bulk in the isolated n-type well.

9. The circuit of claim 8 , further comprising an additional bias for biasing the isolated n-type well at a voltage level at least as high as a voltage at the p-type region and a voltage at the common bulk.

10. The circuit of claim 1 , wherein the voltage multiplier circuit further includes:
third and fourth intermediate nodes that are capacitively coupled to receive opposite phases of a second clock signal, respectively; and
a third transistor and a fourth transistor connected in a cross-coupled configuration, wherein a first conduction terminal of the third transistor and a gate terminal of the fourth transistor are connected to the first intermediate node and wherein a first conduction terminal of the fourth transistor and a gate terminal of the third transistor are connected to the second intermediate node;
wherein said third and fourth transistors have a same conductivity type and share said common bulk that is not tied to a source of either of said third and fourth transistors.

11. The circuit of claim 10 , wherein said first through fourth transistors are implemented in a triple well technology including a p-type region, an isolated n-type well in the p-type region and a p-type well forming said common bulk in the isolated n-type well.

12. The circuit of claim 11 , further comprising an additional bias for biasing the isolated n-type well at a voltage level at least as high as a voltage at the p-type region and a voltage at the common bulk.

13. The circuit of claim 10 , wherein the first and second clock signals have aligned phases.

14. The circuit of claim 1 , wherein the voltage multiplier circuit further includes:
a first node configured to receive a first voltage when said voltage multiplier circuit is configured for operation in a positive voltage boosting mode and configured to output a negative voltage when said circuit is configured for operation in a negative voltage boosting mode; and
a second node configured to output a positive voltage in excess of said first voltage when said voltage multiplier circuit is configured for operation in the positive voltage boosting mode and configured to receive a second voltage in excess of said negative voltage when said circuit is configured for operation in a negative voltage boosting mode;
wherein source-drain paths of said first and second transistors are coupled between the first and second nodes.

15. The circuit of claim 14 , wherein said bias generator circuit is coupled to receive the first voltage from the first node and the second voltage from the second node, said bias generator circuit configured to apply a lower one of the first and second voltages to the common bulk.

16. The circuit of claim 14 , wherein said bias generator circuit comprises: a first biasing transistor and a second biasing transistor having source-drain paths coupled in series between the first and second nodes at a common source and wherein gates of the first and second biasing transistors are cross-coupled to drains of the second and first biasing transistors, respectively.

17. The circuit of claim 16 , wherein the first and second biasing transistors have the same conductivity type as the first and second transistors of the voltage multiplier circuit.

18. The circuit of claim 17 , wherein the first and second biasing transistors have sources and drains formed in the common bulk with sources and drains of the first and second transistors of the voltage multiplier circuit.

19. A circuit, comprising:
a first node;
a second node;
a first transistor and second transistor connected in a cross-coupled configuration, wherein the first transistor is coupled between the first node and a first intermediate node and the second transistor is coupled between the first node and a second intermediate node;
wherein the first and second intermediate nodes are capacitively coupled to receive opposite phases of a first clock signal, respectively;
a third transistor coupled between the first intermediate node and the second node;
a fourth transistor coupled between the second intermediate node and the second node;
wherein the first through fourth transistors share a common bulk that is not tied to a source of any transistor in said first through fourth transistors; and
a bias generator circuit coupled to receive a first voltage from the first node and a second voltage from the second node, said bias generator circuit configured to apply a lower one of the first and second voltages to the common bulk.

20. The circuit of claim 19 , wherein the first through fourth transistors are all n-channel MOS transistors.

21. The circuit of claim 20 , wherein said first through fourth transistors are implemented in a triple well technology including a p-type region, an isolated n-type well in the p-type region and a p-type well forming said common bulk in the isolated n-type well.

22. The circuit of claim 21 , further comprising an additional bias for

Assignees

• St Microelectronics Int Nv

Inventors

• Rana Vikas

Classifications

• H03K19/096

  Synchronous circuits, i.e. using clock signals {(H03K19/01728, H03K19/01855 take precedence)} · CPC title

• G05F1/10

  Regulating voltage or current  (G05F1/02 takes precedence) · CPC title

• H02M3/078

  with means for reducing the back bias effect, i.e. the effect which causes the threshold voltage of transistors to increase as more stages are added to the converters · CPC title

• H02M3/07 Primary

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H02M2003/078

  Electricity · mapped topic