Semiconductor device and manufacturing method thereof

US10811371B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10811371-B2
Application numberUS-201816218352-A
CountryUS
Kind codeB2
Filing dateDec 12, 2018
Priority dateJan 14, 2016
Publication dateOct 20, 2020
Grant dateOct 20, 2020

How to read this patent

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A semiconductor device includes: a semiconductor substrate; a semiconductor layer on the semiconductor substrate; a source electrode and a drain electrode spaced apart from each other on the semiconductor layer; a gate electrode on the semiconductor layer between the source electrode and the drain electrode; and an insulating film covering the semiconductor layer, the source electrode, the drain electrode and the gate electrode, the gate electrode has an eaves structure including a lower electrode joined to the semiconductor layer and an upper electrode provided on the lower electrode and wider than the lower electrode, a principal ingredient of the insulating film is an oxide film where atomic layers are alternately arrayed for each monolayer, and a film thickness of the insulating film that covers the lower electrode of the gate electrode is equal to a film thickness of the insulating film that covers the upper electrode.

First claim

Opening claim text (preview).

The invention claimed is: 1. A semiconductor device comprising: a semiconductor chip; a package in which the semiconductor chip is mounted; and an insulating film covering all exposed portions of the package, wherein a principal ingredient of the insulating film is an oxide film where atomic layers are alternately arrayed for each monolayer, and the principal ingredient of the insulating film is a layered structure of a Ta oxide film and a Si oxide film.

Assignees

Inventors

Classifications

  • between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

  • for monolithic microwave integrated circuits [MMIC] · CPC title

  • the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

  • by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation · CPC title

  • using moulds · CPC title

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Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10811371B2 cover?
A semiconductor device includes: a semiconductor substrate; a semiconductor layer on the semiconductor substrate; a source electrode and a drain electrode spaced apart from each other on the semiconductor layer; a gate electrode on the semiconductor layer between the source electrode and the drain electrode; and an insulating film covering the semiconductor layer, the source electrode, the drai…
Who is the assignee on this patent?
Mitsubishi Electric Corp
What technology area does this patent fall under?
Primary CPC classification H10W42/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 20 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).