Buffer layer to prevent etching by photoresist developer

Patent metadata

Field	Value
Publication number	US-10811276-B2
Application number	US-201616332998-A
Country	US
Kind code	B2
Filing date	Sep 13, 2016
Priority date	Sep 13, 2016
Publication date	Oct 20, 2020
Grant date	Oct 20, 2020

Abstract

A method includes: providing a device having a first layer and a second layer in contact with a surface of the first layer, in which the second layer includes a first superconductor material; forming a buffer material on the second layer to form an etch buffer layer, in which an etch rate selectivity of the buffer material relative to the second layer upon exposure to a photoresist developer is such that the underlying second layer is not etched during exposure of the buffer layer to the photoresist developer; depositing and removing a selected portion of a resist layer to uncover a first portion of the etch buffer layer, wherein removing the selected portion of the resist layer comprises applying the photoresist developer to the selected portion of the resist layer.

First claim

What is claimed is:

1. A method of fabricating a quantum circuit device, the method comprising:
providing a device having a first layer and a second layer in contact with a surface of the first layer, wherein the second layer comprises a first superconductor material that exhibits superconducting properties at or below a corresponding superconducting critical temperature;
forming a buffer material on a surface of the second layer to form an etch buffer layer, wherein an etch rate selectivity of the buffer material relative to the second layer upon exposure to a photoresist developer is such that the underlying second layer is not etched during exposure of the buffer layer to the photoresist developer;
depositing and removing a selected portion of a resist layer to uncover a first portion of the etch buffer layer, wherein removing the selected portion of the resist layer comprises applying the photoresist developer to the selected portion of the resist layer;
removing the uncovered first portion of the etch buffer layer to uncover a first portion of the second layer; and
forming a dielectric material or a second superconductor material, which exhibits superconducting properties at or below a corresponding superconducting temperature, on the uncovered first portion of the second layer, wherein the second layer and the dielectric material or the second layer and the second superconductor material form part of the quantum circuit device, and wherein the quantum circuit device comprises a parallel plate capacitor or a microstrip resonator.

2. The method of claim 1 , wherein the etch rate selectivity of the buffer material relative to the second layer upon exposure to the photoresist developer is less than 1:2.

3. The method of claim 1 , wherein the first superconductor material of the second layer is aluminum.

4. The method of claim 1 , wherein the buffer material comprises a polymer.

5. The method of claim 4 , wherein the polymer comprises polymethylmethacrylate (PMMA).

6. The method of claim 1 , wherein removing the uncovered first portion of the etch buffer layer comprises subjecting the uncovered first portion of the etch buffer layer to a dry etch.

7. The method of claim 6 , wherein the dry etch comprises an O 2 plasma.

8. The method of claim 1 , further comprising removing, subsequent to depositing the dielectric material or the second superconductor material, a remaining portion of the resist layer and the etch buffer layer.

9. The method of claim 1 , wherein the first layer comprises a substrate.

10. The method of claim 9 , wherein the substrate comprises a silicon wafer or a sapphire wafer.

Assignees

• Google Llc

Inventors

• Megrant Anthony Edward

Classifications

• H10D64/01304

  characterised by the conductor · CPC title

• H10W20/064

  by modifying the conductivity of conductive parts, e.g. by alloying · CPC title

• H10P14/40 Primary

  of conductive or resistive materials · CPC title

• H10D64/608

  being superconducting · CPC title

• G03F7/094

  Multilayer resist systems, e.g. planarising layers · CPC title