Display device

US10810939B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10810939-B2
Application numberUS-201916521678-A
CountryUS
Kind codeB2
Filing dateJul 25, 2019
Priority dateDec 21, 2015
Publication dateOct 20, 2020
Grant dateOct 20, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display device related to one embodiment of the present invention includes a plurality of pixel circuits each connected to a scanning signal line, initialization control signal line, light emitting control signal line and video signal line, wherein each of the plurality of pixel circuits includes a first transistor connected to the scanning signal line and the video signal line, a second transistor connected to a first node and the first transistor, a third transistor connected to the first node and a scanning signal line, a fourth transistor connected to the second transistor and the light emitting control signal line, and a fifth transistor connected to the second transistor, a power supply voltage line, and the light emitting control signal line.

First claim

Opening claim text (preview).

What is claimed is: 1. A display device comprising: a plurality of first scanning signal lines; a plurality of second scanning signal lines; a plurality of initialization control signal lines; a plurality of light emitting control signal lines; a plurality of video signal lines arranged intersecting the plurality of first scanning signal lines, the plurality of second scanning signal lines, the plurality of initialization control signal lines, and the plurality of light emitting control signal lines; and a plurality of pixel circuit groups each connected to one of the first scanning signal lines, one of the second scanning signal lines, one of the initialization control signal lines, one of the light emitting control signal lines, and one of the video signal lines; wherein each of the plurality of pixel circuit groups includes: a first pixel circuit; a second pixel circuit; a first switch which includes a control terminal connected to the light emitting control signal line and is connected between a power supply voltage line and a second node; and a fifth switch which includes a control terminal connected to the first scanning signal line and is connected between the video signal line and the second node; the first pixel circuit includes: a second switch which includes a control terminal connected to a first node, a first terminal connected to the second node, and a second terminal connected to a third node; a third switch which includes a control terminal connected to the second scanning signal line and is connected between the first node and the third node; a fourth switch which includes a control terminal connected to the light emitting control signal line and is connected between the third node and a light emitting element; a storage capacitor including a first terminal connected to the first node, and a second terminal connected to the initialization control signal line; and the light emitting element, and the second pixel circuit includes: another second switch including a control terminal connected to another first node, a first terminal connected to the second node, and a second terminal connected to another third node; another third switch which includes a control terminal connected to the second scanning signal line and is connected between the another first node and the another third node; another fourth switch which includes a control terminal connected to the light emitting control signal line and is connected between the another third node and another light emitting element; another storage capacitor including a first terminal connected to the another first node, and a second terminal connected to the initialization control signal line; and the another light emitting element. 2. The display device according to claim 1 , further comprising: a drive circuit outputting a signal to the first scanning signal line, the second scanning signal line, the initialization control signal line, the light emitting control signal line, and the video signal line; wherein the drive circuit supplies a signal to the control terminal of the third switch to turn the third switch OFF in an initialization period, and the drive circuit changes a voltage of the second terminal of the storage capacitor by changing the initialization control signal line to a first voltage so that the third switch changes to ON in the initialization period. 3. The display device according to claim 2 , wherein the drive circuit changes a voltage of the second terminal of the storage capacitor by changing the initialization control signal line to a second voltage lower than the first voltage in a writing and threshold compensation period after the initialization period, and the drive circuit turns the third switch to ON in sequence and supplies gradation data in sequence to the video signal line in a state where a signal for turning the fifth switch to ON is supplied to the first scanning signal line in the writing and threshold compensation period. 4. The display device according to claim 3 , wherein the drive circuit changes the first switch and fourth switch to ON in light emitting period after the writing and threshold compensation period in a state where a signal for turning the third switch and fifth switch to OFF is supplied to the first scanning signal line, and the drive circuit supplies a current to the light emitting element to emit light from the light emitting element in the light emitting period. 5. The display device according to claim 1 , wherein the first, third, fourth and fifth switches are transistors, and the first, third, fourth and fifth switches and the second transistor are transistors having the same polarity. 6. The display device according to claim 5 , wherein the first, third, fourth and fifth switches and the second transistor are P channel transistors. 7. The display device according to claim 1 , wherein a number of the first scanning lines is less than a number of the second scanning lines, a number of the initialization control signal lines is less than the number of the second scanning lines, and a number of the light emitting control signal lines is less than the number of the second scanning lines. 8. The display device according to claim 1 , wherein a signal from the light emitting control signal line to the control terminal of the first switch controls whether the first switch is an electrical connection state or an electrical disconnection state, a signal from the first scanning signal line to the control terminal of the fifth switch controls whether the fifth switch is an electrical connection state or an electrical disconnection state, a signal from the second scanning signal line to the control terminal of the third switch controls whether the third switch is an electrical connection state or an electrical disconnection state, and the signal from the light emitting control signal line to the control terminal of the fourth switch controls whether the fourth switch is an electrical connection state or an electrical disconnection state. 9. A display device comprising: a plurality of first scanning signal lines; a plurality of second scanning signal lines; a plurality of initialization control signal lines; a plurality of light emitting control signal lines; a plurality of video signal lines arranged intersecting the plurality of first scanning signal lines, the plurality of second scanning signal lines, the plurality of initialization control signal lines, and the plurality of light emitting control signal lines; and a plurality of pixel circuit groups each connected to one of the first scanning signal lines, two of the second scanning signal lines, one of the initialization control signal lines, one of the light emitting control signal lines, and one of the video signal lines; wherein each of the plurality of pixel circuit groups includes: a first pixel circuit; a second pixel circuit; a first switch which includes a control terminal connected to the light emitting control signal line and is connected between a power supply voltage line and a second node; and a fifth switch which includes a control terminal connected to the first scanning signal line and is connected between the video signal line and the second node; the first pixel circuit includes: a second switch which includes a control terminal connected to a first node, a first terminal connected to the second node, and a second terminal connected to a third node; a third switch which includes a control terminal connected to the second scanning signal line and is connected between the first node and the third node; a fourth switch which includes a control terminal connected to the light emitti

Assignees

Inventors

Classifications

  • in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements · CPC title

  • Clearing or presetting the whole screen independently of waveforms, e.g. on power-on (G09G2310/063 takes precedence) · CPC title

  • Details of timing specific for flat panels, other than clock recovery · CPC title

  • with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

  • G09G3/3233Primary

    with pixel circuitry controlling the current through the light-emitting element · CPC title

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Frequently asked questions

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What does patent US10810939B2 cover?
A display device related to one embodiment of the present invention includes a plurality of pixel circuits each connected to a scanning signal line, initialization control signal line, light emitting control signal line and video signal line, wherein each of the plurality of pixel circuits includes a first transistor connected to the scanning signal line and the video signal line, a second tran…
Who is the assignee on this patent?
Japan Display Inc
What technology area does this patent fall under?
Primary CPC classification G09G3/3233. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Oct 20 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).