Flush strategy for using DRAM as cache media system and method

Patent metadata

Field	Value
Publication number	US-10810123-B1
Application number	US-201715792888-A
Country	US
Kind code	B1
Filing date	Oct 25, 2017
Priority date	Oct 25, 2017
Publication date	Oct 20, 2020
Grant date	Oct 20, 2020

Abstract

A method, computer program product, and computer system for receiving, by a computing device, an I/O request. The I/O request may be processed as a write miss I/O. One or more dirty pages associated with the write miss I/O may be placed into a tree according to a key. It may be determined whether one of a first event and a second event occurs. A data flush may be triggered for the tree when the first event occurs, and the data flush may be triggered for the data flush for the tree when the second event occurs.

First claim

What is claimed is:

1. A computer-implemented method comprising:
receiving, by a computing device, an I/O request;
processing the I/O request as a write miss I/O, wherein processing the I/O request as a write miss I/O includes searching a hash table;
allocating at least one free cache page from a cache free page queue;
transferring data associated with the write miss I/O into a dynamic random access memory;
writing one or more dirty pages associated with the write miss I/O to a first non-volatile memory express device and a second non-volatile memory express device, wherein the first non-volatile memory device and second non-volatile memory device are two different devices;
updating a status of the at least one free cache page, wherein updating a status of the at least one free cache page includes inserting the one or more dirty pages associated with the write miss I/O into the hash table;
placing the one or more dirty pages associated with the write miss I/O into a tree according to a key;
determining whether one of a first event and a second event occurs; and
triggering a data flush for the tree when the first event occurs, and triggering the data flush for the tree when the second event occurs.

2. The computer-implemented method of claim 1 wherein the tree includes a red-black tree.

3. The computer-implemented method of claim 2 wherein a leaf of the red-black tree is a set of the one or more dirty pages.

4. The computer-implemented method of claim 3 wherein the key of the red-black tree includes content associated with a logical unit number and a logical block address.

5. The computer-implemented method of claim 1 wherein the first event includes a node of the tree being completely filled with dirty pages.

6. The computer-implemented method of claim 1 wherein the second event includes reaching a threshold amount of free pages in a cache.

7. The computer-implemented method of claim 6 further comprising combining two nodes in the tree that have sequential logical block addresses for the data flush.

8. A computer program product residing on a non-transitory computer readable storage medium having a plurality of instructions stored thereon which, when executed across one or more processors, causes at least a portion of the one or more processors to perform operations comprising:
receiving, by a computing device, an I/O request;
processing the I/O request as a write miss I/O, wherein processing the I/O request as a write miss I/O includes searching a hash table;
allocating at least one free cache page from a cache free page queue;
transferring data associated with the write miss I/O into a dynamic random access memory;
writing one or more dirty pages associated with the write miss I/O to a first non-volatile memory express device and a second non-volatile memory express device, wherein the first non-volatile memory device and second non-volatile memory device are two different devices;
updating a status of the at least one free cache page, wherein updating a status of the at least one free cache page includes inserting the one or more dirty pages associated with the write miss I/O into the hash table;
placing the one or more dirty pages associated with the write miss I/O into a tree according to a key;
determining whether one of a first event and a second event occurs; and
triggering a data flush for the tree when the first event occurs, and triggering the data flush for the tree when the second event occurs.

9. The computer program product of claim 8 wherein the tree includes a red-black tree.

10. The computer program product of claim 9 wherein a leaf of the red-black tree is a set of the one or more dirty pages.

11. The computer program product of claim 10 wherein the key of the red-black tree includes content associated with a logical unit number and a logical block address.

12. The computer program product of claim 8 wherein the first event includes a node of the tree being completely filled with dirty pages.

13. The computer program product of claim 8 wherein the second event includes reaching a threshold amount of free pages in a cache.

14. The computer program product of claim 13 wherein the operations further comprise combining two nodes in the tree that have sequential logical block addresses for the data flush.

15. A computing system including one or more processors and one or more memories configured to perform operations comprising:
receiving, by a computing device, an I/O request;
processing the I/O request as a write miss I/O, wherein processing the I/O request as a write miss I/O includes searching a hash table;
allocating at least one free cache page from a cache free page queue;
transferring data associated with the write miss I/O into a dynamic random access memory;
writing one or more dirty pages associated with the write miss I/O to a first non-volatile memory express device and a second non-volatile memory express device, wherein the first non-volatile memory device and second non-volatile memory device are two different devices;
updating a status of the at least one free cache page, wherein updating a status of the at least one free cache page includes inserting the one or more dirty pages associated with the write miss I/O into the hash table;
placing the one or more dirty pages associated with the write miss I/O into a tree according to a key;
determining whether one of a first event and a second event occurs; and
triggering a data flush for the tree when the first event occurs, and triggering the data flush for the tree when the second event occurs.

16. The computing system of claim 15 wherein the tree includes a red-black tree.

17. The computing system of claim 16 wherein a leaf of the red-black tree is a set of the one or more dirty pages.

18. The computing system of claim 17 wherein the key of the red-black tree includes content associated with a logical unit number and a logical block address.

19. The computing system of claim 15 wherein the first event includes a node of the tree being completely filled with dirty pages and wherein the second event includes reaching a threshold amount of free pages in a cache.

20. The computing system of claim 19 wherein the operations further comprise combining two nodes in the tree that have sequential logical block addresses for the data flush.

Assignees

• Emc Ip Holding Co Llc

Inventors

• Xu Xinlei
• Gao Jian
• Yang Lifeng
• Wahl Michael P

Classifications

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F13/1636 Primary

  using refresh · CPC title

• G06F2212/7203

  Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title