Systems and methods of detecting power bugs

Patent metadata

Field	Value
Publication number	US-10810071-B2
Application number	US-201916539794-A
Country	US
Kind code	B2
Filing date	Aug 13, 2019
Priority date	Jun 25, 2013
Publication date	Oct 20, 2020
Grant date	Oct 20, 2020

Abstract

Embodiments of the present invention provide a system and methods for detecting power bugs. In one embodiment, a computer-implemented method for analyzing a computer code includes generating a control flow graph for at least a portion of the computer code at a processor. The method further includes identifying power bugs by traversing the control flow graph if the control flow graph exits without performing a function call to deactivate power to any component of a device configured to execute computer executable instructions based on the computer code after performing a function call to activate power.

First claim

The invention claimed is:

1. A computer-implemented method for analyzing a computer code, the method comprising:
at a processor, generating a control flow graph for at least a portion of the computer code; and
identifying power bugs by traversing the control flow graph to identify if the control flow graph exits without performing a function call to deactivate power to any component of a device configured to execute computer executable instructions based on the computer code after performing a function call to activate power, wherein traversing the control flow graph comprises:
identifying steps in the control flow graph relating to function calls for activating or deactivating power,
defining a power variable for each step with a function call for activation and for each step with a function call for deactivation that are identified,
assigning a first binary value to the power variable for each function call for activation and assigning an opposite second binary value to the power variable for each function call for deactivation,
generating a set of definitions of the power variable reaching an EXIT block of the control flow graph, and
identifying a power bug if any definition of the first binary value is identified in the set of definitions of the power variable at the EXIT block.

2. The method of claim 1 , further comprising generating an error message if the control flow graph exits without performing a function call to deactivate power to any component.

3. The method of claim 2 , further comprising storing the error message in a non-transitory memory medium.

4. The method of claim 1 , wherein the computer executable instructions are configured to run on a power constrained device.

5. The method of claim 4 , wherein the function call to activate power comprises a function call to prevent the power constrained device from going to sleep, and wherein the function call to deactivate power comprises a function call to re-allow the power constrained device to go to sleep.

6. The method of claim 4 , further comprising:
receiving the computer code; and
removing the identified power bugs.

7. The method of claim 6 , further comprising:
after removing the identified power bugs, generating the computer executable instructions by compiling the computer code if the computer code exits after performing a function call to deactivate power to any component previously activated; and
storing the computer executable instructions in a non-transitory memory medium.

8. The method of claim 7 , further comprising:
providing an application comprising the computer executable instructions to a user device at an online market place.

9. The method of claim 1 , wherein the traversing the control flow graph comprises:
applying a reaching definitions analysis to identify any mismatch in definitions relating to function calls for activating or deactivating power.

10. The method of claim 1 , wherein the traversing the control flow graph comprises applying a live variable analysis, or an available expressions analysis.

11. The method of claim 1 , wherein the computer code is configured to execute as a single thread process.

12. The method of claim 1 , wherein generating the control flow graph comprises:
generating individual control flow graph for each event handler in the computer code comprising a plurality of event handlers; and
stitching together the individual control flow graphs.

13. The method of claim 1 , wherein computer code is configured to execute as a multi-threaded application.

14. The method of claim 13 , wherein generating the control flow graph comprises generating a control flow graph for a multi-threaded application.

15. The method of claim 14 , wherein generating the control flow graph comprises:
generating individual control flow graph for each thread;
connecting a fork spawning each thread with an ENTRY block of the individual control flow graph for that thread; and
connecting an EXIT block of the individual control flow graph for that thread with a join node or with another ENTRY block of another individual control flow graph of another thread.

16. A computing device comprising:
a processor configured to execute a debugging tool, the debugging tool configured to:
generate a control flow graph for at least a portion of a computer code, and
identify power bugs by detecting if the control flow graph exits without performing a function call for deactivating power to any component of a device configured to execute computer executable instructions based on the computer code by traversing the control flow graph after performing a function call to activate power, wherein traversing the control flow graph comprises:
identify steps in the control flow graph relating to function calls for activating or deactivating power,
define a power variable for each step with a function call for activation and for each step with a function call for deactivation that are identified,
assign a first binary value to the power variable for each function call for activation and assigning an opposite second binary value to the power variable for each function call for deactivation,
generate a set of definitions of the power variable reaching an EXIT block of the control flow graph, and
identify a power bug if any definition of the first binary value is identified in the set of definitions of the power variable at the EXIT block.

17. The computing device of claim 16 , wherein the traversing the control flow graph comprises:
apply a reaching definitions analysis to identify any mismatch in definitions relating to function calls for activating or deactivating power.

18. A non-transitory storage medium, comprising:
a debugging tool, the debugging tool configured to analyze a computer code by:
generating a control flow graph for at least a portion of the computer code; and
identifying power bugs by detecting if the control flow graph exits without performing a function call for deactivating power to any component of a device configured to execute computer executable instructions based on the computer code by traversing the control flow graph after performing a function call to activate power, wherein traversing the control flow graph comprises:
identify steps in the control flow graph relating to function calls for activating or deactivating power,
define a power variable for each step with a function call for activation and for each step with a function call for deactivation that are identified,
assign a first binary value to the power variable for each function call for activation and assigning an opposite second binary value to the power variable for each function call for deactivation,
generate a set of definitions of the power variable reaching an EXIT block of the control flow graph, and
identify a power bug if any definition of the first binary value is identified in the set of definitions of the power variable at the EXIT block.

Assignees

• Purdue Research Foundation

Inventors

• Hu Yu Charlie
• Jindal Abhilash
• Midkiff Samuel
• Pathak Abhinav

Classifications

• G06F11/3604 Primary

  Analysis of software for verifying properties of programs (testing of software G06F11/3668) · CPC title

• G06F11/3698

  Environments for analysis, debugging or testing of software · CPC title

• G06F11/0751

  Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06) · CPC title

• G06F11/3466

  Performance evaluation by tracing or monitoring · CPC title

• G06F8/433

  Dependency analysis; Data or control flow analysis · CPC title