Multi-level logic analyzer for analyzing multi-level digital signals and method for operating a multi-level logic analyzer for analyzing multi-level digital signals

Patent metadata

Field	Value
Publication number	US-10809282-B2
Application number	US-201715823841-A
Country	US
Kind code	B2
Filing date	Nov 28, 2017
Priority date	Mar 23, 2017
Publication date	Oct 20, 2020
Grant date	Oct 20, 2020

Abstract

A multi-level logic analyzer for analyzing multi-level digital signals comprises a plurality of signal inputs, each signal input being configured to receive a multi-level digital signal, a plurality of comparison units, each comparison unit comprising a first comparator input and a second comparator input and being configured to compare a signal received at the first comparator input with a signal received at the second comparator input, and first switching means configured to couple at least one of the signal inputs with the first comparator inputs of at least two of the comparison units.

First claim

The invention claimed is:

1. A multi-level logic analyzer for analyzing multi-level digital signals, the multi-level logic analyzer comprising:
a plurality of signal inputs, each signal input being configured to receive a multi-level digital signal,
a plurality of signal outputs, each signal output being configured to output an output signal;
a plurality of comparison units, each comparison unit comprising a first comparator input and a second comparator input and being configured to compare a signal received at the first comparator input with a signal received at the second comparator input,
first switching means configured to couple at least one of the signal inputs with the first comparator inputs of at least two of the comparison units, and
second switching means configured to controllably couple comparison units that are coupled on their first comparison input with the same signal input on their output side with one of the signal outputs, and
wherein the signal outputs comprise an encoder that encodes output signals of the comparison units that are connected to the respective signal output into binary values or serializes the output signals of the respective comparison units.

2. The multi-level logic analyzer according to claim 1 , wherein the second switching means are further configured to controllably couple comparison units that are coupled on their input side with a single signal input on their output side with different signal outputs.

3. The multi-level logic analyzer according to claim 1 , comprising a plurality of configurable threshold voltage sources, each threshold voltage source being configured to provide a configured output voltage.

4. The multi-level logic analyzer according to claim 3 , comprising a plurality of third switching means being configured to couple one of the threshold voltage sources with at least two of the comparison units, especially when the respective two of the comparison units are coupled to different signal inputs.

5. The multi-level logic analyzer according to claim 3 , wherein the threshold voltage sources are configured to each output a different threshold voltage.

6. The multi-level logic analyzer according to claim 1 , wherein the first switching means are further configured to couple one of the signal inputs with a first comparator input of one of the comparison units and one of the signal inputs with the second comparator input of the respective comparison unit.

7. A Method for operating a multi-level logic analyzer for analyzing multi-level digital signals, the method comprising:
receiving multi-level digital signals, each with a signal input,
controllably coupling at least one of the signal inputs with first comparator inputs of at least two comparison units, each comparison unit comprising a first comparator input and a second comparator input,
comparing the signal received at the first comparator input of a respective comparison unit with a signal received at the second comparator input of a respective comparison unit,
output an output signal with a plurality of signal out-puts, and
controllably coupling comparison units that are coupled on their first comparison input with the same signal input on their output side with one of the signal outputs, and
encoding the output signals of the comparison units that are connected to one of the signal outputs into binary values or serializing the output signals of the respective comparison units, especially in the respective signal outputs.

8. The method according to claim 7 , comprising controllably coupling comparison units that are coupled on their input side with a single signal input on their output side with different signal outputs.

9. The method according to claim 7 , comprising providing configured output voltages with a plurality of configurable threshold voltage sources.

10. The method according to claim 9 , comprising coupling one of the threshold voltage sources with at least two of the comparison units, especially when the respective two of the comparison units are coupled to different signal inputs.

11. The method according to claim 9 , wherein the threshold voltage sources each output a different threshold voltage.

12. The method according to claim 7 , comprising coupling one of the signal inputs with a first comparator input of one of the comparison units and one of the signal inputs with the second comparator input of the respective comparison unit.

Assignees

• Rohde & Schwarz

Inventors

• Peschke Martin

Classifications

• G01R29/02 Primary

  Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration · CPC title

• G01R31/3177

  Testing of logic operation, e.g. by logic analysers · CPC title

• G01R13/0272 Primary

  for sampling · CPC title

• G01R31/00 Primary

  Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere ({measuring superconductive properties G01R33/1238;} testing line transmission systems H04B3/46; testing or measuring semiconductors or solid state devices during manufacture {H10P74/00}) · CPC title

• H04L25/4917

  using multilevel codes · CPC title