Resistive random access memory and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10804465-B2
Application number	US-201816123234-A
Country	US
Kind code	B2
Filing date	Sep 6, 2018
Priority date	Sep 7, 2017
Publication date	Oct 13, 2020
Grant date	Oct 13, 2020

Abstract

A resistive random access memory and a manufacture method thereof are provided. The resistive random access memory includes: a first electrode, a second electrode, a resistive layer between the first electrode and the second electrode, and at least one thermal enhanced layer; the thermal enhanced layer is adjacent to the resistive layer, and a thermal conductivity of the thermal enhanced layer is less than a thermal conductivity of the first electrode and a thermal conductivity of the second electrode.

First claim

What is claimed is:

1. A resistive random access memory, comprising:
a first electrode;
a second electrode;
a resistive layer between the first electrode and the second electrode; and
a plurality of thermal enhanced layers, wherein the plurality of thermal enhanced layers is adjacent to the resistive layer, a thermal conductivity of the plurality of thermal enhanced layers is less than a thermal conductivity of the first electrode and a thermal conductivity of the second electrode, and the plurality of thermal enhanced layers is configured to preserve heat generated by the resistive layer,
the plurality of thermal enhanced layers and the resistive layer are independent of each other,
the plurality of thermal enhanced layers are on a top side of the resistive layer, and on a bottom side of the resistive layer, and on lateral sides of the resistive layer, respectively, the top side and the bottom side of the resistive layer are respectively two sides of the resistive layer in a direction in which the first electrode and the second electrode are stacked, and the lateral sides of the resistive layer are two sides of the resistive layer in a direction perpendicular to the direction in which the first electrode and the second electrode are stacked.

2. The resistive random access memory according to claim 1 , wherein the thermal conductivity of the first electrode and/or the thermal conductivity of the second electrode are/is twice, five times or more than ten times as high as the thermal conductivity of the plurality of thermal enhanced layers.

3. The resistive random access memory according to claim 1 , wherein the thermal conductivity of a material of the plurality of thermal enhanced layers ranges from 0.01 W·m −1 ·K −1 to 20 W·m −1 ·K −1 .

4. The resistive random access memory according to claim 1 , further comprising a substrate,
wherein the first electrode, the second electrode, the resistive layer, and the plurality of thermal enhanced layers are on the substrate.

5. The resistive random access memory according to claim 4 , wherein a material of the substrate comprises silicon and/or silicon oxide.

6. The resistive random access memory according to claim 1 , wherein a material of the first electrode and/or a material of the second electrode comprises Ti, Al, Ni, Ag, Au, W, Cu, Pt, Pd or TiN.

7. The resistive random access memory according to claim 1 , wherein a material of the resistive layer comprises transition metal oxide.

8. The resistive random access memory according to claim 7 , wherein the transition metal oxide comprises AlO x , TaO x , HfO x , SiO x , TiO x or WO x .

9. The resistive random access memory according to claim 1 , wherein a thickness of the resistive layer ranges from 1 nm to 30 nm.

10. The resistive random access memory according to claim 1 , wherein an electrical conductivity of a material of the plurality of thermal enhanced layers ranges from 10 μΩ/cm 2 to 10 Ω/cm 2 .

11. The resistive random access memory according to claim 1 , wherein a material of the plurality of thermal enhanced layers comprises anoxic metal oxide or a phase change material.

12. The resistive random access memory according to claim 11 , wherein the anoxic metal oxide comprises AlO x , HfO x , SiO x , TiO x , TaO x or WO x ; alternatively, the phase change material comprises Ge 2 Sb 2 Te 5 .

13. The resistive random access memory according to claim 1 , wherein a thickness of the plurality of thermal enhanced layers ranges from 10 nm to 200 nm.

Assignees

• Univ Tsinghua

Inventors

• Wu Huaqiang
• Wu Wei
• Gao Bin
• Qian He

Classifications

• H01L45/144

  Electricity · mapped topic

• H01L45/146

  Electricity · mapped topic

• H01L45/128 Primary

  Electricity · mapped topic

• H01L45/06

  Electricity · mapped topic

• H01L45/1608

  Electricity · mapped topic