Semiconductor device

Patent metadata

Field	Value
Publication number	US-10804388-B2
Application number	US-201716071322-A
Country	US
Kind code	B2
Filing date	Jan 16, 2017
Priority date	Jan 20, 2016
Publication date	Oct 13, 2020
Grant date	Oct 13, 2020

Abstract

A semiconductor device 1 includes a trench gate structure 6 formed in a surface layer portion of a first principal surface of a semiconductor layer. A source region 10 and a well region 11 are formed in a surface layer portion of the first principal surface of the semiconductor layer at a side of the trench gate structure 6. The well region 11 is formed in a region at a side of the second principal surface of the semiconductor layer with respect to the source region 10. A channel is formed along the trench gate structure 6 in a portion of the well region 11. A multilayer region 22 is formed in a region between the trench gate structure 6 and the source region 10 in the semiconductor layer. The multilayer region 22 has a p type impurity region 20 formed in the surface layer portion of the first principal surface of the semiconductor layer and an n type impurity region 21 formed in a side of the second principal surface of the semiconductor layer with respect to the second conductivity type impurity region 20.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor layer of a first conductivity type having a first principal surface and a second principal surface;
a trench gate structure including a gate trench formed in the surface layer portion of the first principal surface of the semiconductor layer and a gate electrode embedded in the gate trench with an insulating film interposed between the gate trench and the gate electrode;
a source region of the first conductivity type formed in the surface layer portion of the first principal surface of the semiconductor layer at a side of the trench gate structure;
a well region of a second conductivity type formed in a region at a side of the second principal surface of the semiconductor layer with respect to the source region along the trench gate structure at a side of the trench gate structure and including a channel formed in a portion along the trench gate structure; and
a multilayer region formed in a region between the trench gate structure and the source region in the semiconductor layer, the multilayer region including a second conductivity type impurity region formed in the surface layer portion of the first principal surface of the semiconductor layer and a first conductivity type impurity region formed in a side of the second principal surface of the semiconductor layer with respect to the second conductivity type impurity region.

2. The semiconductor device according to claim 1 , wherein the second conductivity type impurity region is in contact with the trench gate structure.

3. The semiconductor device according to claim 1 or 2 , wherein the source region is connected to the well region,
the second conductivity type impurity region is connected to the source region in a lateral direction parallel to the first principal surface of the semiconductor layer, and
the first conductivity type impurity region is connected to the source region in the lateral direction parallel to the first principal surface of the semiconductor layer.

4. The semiconductor device according to claim 1 , wherein the first conductivity type impurity region has an extended portion extending in a region below the source region.

5. The semiconductor device according to claim 1 , further comprising a source electrode formed at the first principal surface of the semiconductor layer and electrically connected to the source region and the second conductivity type impurity region.

6. The semiconductor device according to claim 1 , wherein the source region is exposed from the first principal surface of the semiconductor layer, and
the second conductivity type impurity region is exposed from the first principal surface of the semiconductor layer.

7. The semiconductor device according to claim 1 , further comprising a trench source structure including a source trench formed in the surface layer portion of the first principal surface of the semiconductor layer spaced from the trench gate structure and a source electrode embedded in the source trench, wherein
the source region is in contact with the trench source structure.

8. The semiconductor device according to claim 7 , wherein the second conductivity type impurity region covers the source region.

9. The semiconductor device according to claim 1 , wherein a metal insulator semiconductor field effect transistor (MISFET) including the semiconductor layer, the trench gate structure, and the multilayer region is formed, and
a junction gate field-effect transistor (JFET) including the source region, the well region, and the multilayer region is formed.

10. The semiconductor device according to claim 9 , wherein the second conductivity type impurity region forms a gate of the JFET and is set at the same potential as a potential of the well region.

11. The semiconductor device according to claim 1 , wherein the trench gate structure extends in a band shape.

12. The semiconductor device according to claim 1 , wherein the plurality of trench gate structures extend in band shapes along the same direction and are formed at intervals.

13. The semiconductor device according to claim 1 , wherein the multilayer region selectively includes a portion without the first conductivity type impurity region.

14. The semiconductor device according to claim 1 , wherein the multilayer region includes a portion with the first conductivity type impurity region and a portion without the first conductivity type impurity region.

15. The semiconductor device according to claim 1 , further comprising a drain electrode connected to the second principal surface of the semiconductor layer.

16. The semiconductor device according to claim 1 , wherein the semiconductor layer includes a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate.

17. The semiconductor device according to claim 1 , wherein the semiconductor layer includes an SiC semiconductor substrate and an SiC epitaxial layer formed on the SiC semiconductor substrate.

Assignees

• Rohm Co Ltd

Inventors

• Nakagawa Minoru
• Mori Seigo
• Sakaguchi Takui
• Aketa Masatoshi
• Nakano Yuki

Classifications

• H10D64/513 Primary

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D64/01

  Manufacture or treatment · CPC title

• H10D62/8325

  Silicon carbide · CPC title

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title

• H10D30/668 Primary

  having trench gate electrodes, e.g. UMOS transistors · CPC title