Gate stack design for GaN e-mode transistor performance

Patent metadata

Field	Value
Publication number	US-10804386-B2
Application number	US-201616306292-A
Country	US
Kind code	B2
Filing date	Jul 1, 2016
Priority date	Jul 1, 2016
Publication date	Oct 13, 2020
Grant date	Oct 13, 2020

Abstract

A gate stack structure is disclosed for inhibiting charge leakage in III-V transistor devices. The techniques are particularly well-suited for use in enhancement-mode MOSHEMTs, but can also be used in other transistor designs susceptible to charge spillover and unintended channel formation in the gate stack. In an example embodiment, the techniques are realized in a transistor having a III-N gate stack over a gallium nitride (GaN) channel layer. The gate stack is configured with a relatively thick barrier structure and wide bandgap III-N materials to prevent or otherwise reduce channel charge spillover resulting from tunneling or thermionic processes at high gate voltages. The barrier structure is configured to manage lattice mismatch conditions, so as to provide a robust high performance transistor design. In some cases, the gate stack is used in conjunction with an access region polarization layer to induce two-dimensional electron gas (2DEG) in the channel layer.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a first layer including a group III-V semiconductor material;
a gate stack over the first layer, and including a second layer of aluminum gallium nitride (AlGaN) between third and fourth layers of aluminum nitride (AlN); and
a first region and a second region each including a group III-V semiconductor and separated from the gate stack by respective third regions,
the third regions including a group III-V semiconductor material.

2. The integrated circuit structure of claim 1 , wherein the first layer is gallium nitride (GaN).

3. The integrated circuit structure of claim 1 , wherein the gate stack further includes:
a gate electrode; and
a gate dielectric structure, wherein the gate dielectric structure is a multi-layer structure including a layer of interface material and a layer of high-k dielectric material, wherein the layer of interface material is a group III-V semiconductor oxide.

4. The integrated circuit structure of claim 1 , wherein the second layer of AlGaN between the third and fourth layers of AlN has an aluminum concentration in the range of 5% to 15%.

5. The integrated circuit structure of claim 1 , wherein the second layer of AlGaN between the third and fourth layers of AlN has a thickness in the range of 1 nm to 3 nm, and the third and fourth layers of AlN each has a thickness in the range of 0.5 nm to 2 nm.

6. The integrated circuit structure of claim 1 , wherein the first and second regions are n-doped and include nitrogen and one or both of gallium and indium.

7. The integrated circuit structure of claim 1 , wherein the group III-V semiconductor material of the third regions includes aluminum and nitrogen.

8. The integrated circuit structure of claim 7 , wherein the group III-V semiconductor material of the third regions further includes indium, and has an aluminum concentration in the range of 80% to 85%.

9. The integrated circuit structure of claim 7 , wherein the group III-V semiconductor material of the third regions further includes gallium, and has an aluminum concentration in the range of 20% to 40%.

10. The integrated circuit structure of claim 1 , wherein the group III-V semiconductor material of the third regions has an aluminum concentration that is greater than the aluminum concentration of the second AlGaN layer between the third and fourth layers of AlN.

11. A system-on-chip comprising the integrated circuit structure of claim 1 .

12. A radio frequency (RF) circuit comprising the integrated circuit structure of claim 1 .

13. A mobile computing system comprising the integrated circuit structure of claim 1 .

14. The integrated circuit structure of claim 1 , wherein the gate stack includes a layer of high-k dielectric material directly on the third layer of AlN.

15. An integrated circuit structure, comprising:
a first layer including gallium nitride (GaN);
a gate stack over the first layer, and including a barrier structure configured with a charge spillover reducing layer on a lattice grading layer, each of the charge spillover reducing layer and lattice grading layer including a different group III-N semiconductor, wherein the lattice grading layer includes aluminum; and
a first region and a second region each including a group III-V semiconductor and separated from the gate stack by respective third regions, wherein the first and second regions are n-doped and include gallium nitride (GaN) or indium gallium nitride (InGaN), and wherein the third regions include a group III-V semiconductor material having
an aluminum concentration that is greater than the aluminum concentration of the lattice grading layer.

16. The integrated circuit structure of claim 15 , wherein the gate stack further includes a gate electrode and a work function tuning structure, wherein the work function tuning structure is a multi-layer structure.

17. The integrated circuit structure of claim 15 , wherein the lattice grading layer comprises aluminum gallium nitride (AlGaN) and the charge spillover reducing layer comprises aluminum nitride (AlN), and wherein the lattice grading layer has a thickness in the range of 1 nm to 3 nm and an aluminum concentration in the range of 5% to 15%, and the charge spillover reducing layer has a thickness in the range of 0.5 nm to 2 nm.

18. The integrated circuit structure of claim 15 , wherein the group III-V semiconductor material of the third regions includes aluminum indium nitride (AlInN), and has an aluminum concentration in the range of 80% to 85%.

19. The integrated circuit structure of claim 15 , wherein the group III-V semiconductor material of the third regions includes aluminum gallium nitride (AlGaN), and has an aluminum concentration in the range of 20% to 40%.

20. The integrated circuit structure of claim 15 , wherein the gate stack includes a layer of high-k dielectric material directly on the charge spillover reducing layer.

Assignees

• Intel Corp

Inventors

• Dasgupta Sansaptak
• Then Han Wui
• Radosavljevic Marko
• Gardner Sanaz K
• Sung Seung Hoon

Classifications

• H10W10/00

  Isolation regions in semiconductor bodies between components of integrated devices · CPC title

• H10W10/01

  Manufacture or treatment · CPC title

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title

• H10D64/602

  Heterojunction gate electrodes for FETs · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title