Semiconductor device and solid-state imaging device

Patent metadata

Field	Value
Publication number	US-10804313-B2
Application number	US-201816001278-A
Country	US
Kind code	B2
Filing date	Jun 6, 2018
Priority date	Oct 4, 2013
Publication date	Oct 13, 2020
Grant date	Oct 13, 2020

Abstract

The present technology relates to a semiconductor device and a solid-state imaging device of which crack resistance can be improved in a simpler way. The semiconductor device has an upper substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and a second substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and is joined to the upper substrate. In addition, a pad for wire bonding or probing is formed in the upper substrate, and pads for protecting corner or side parts of the pad for wire bonding or probing are radially laminated and provided in each of the wiring layers between the pad and the Si substrate of the lower substrate. The present technology can be applied to a solid-state imaging device.

First claim

What is claimed is:

1. An imaging device, comprising:
a first semiconductor section, including:
a first semiconductor substrate including a photodiode and a transfer transistor in a pixel array region; and
a first wiring layer including a first metal pad, a second metal pad, and a first inter-layer insulating film,
wherein the first metal pad and the second metal pad are disposed at a first side of the first wiring layer opposite to a light incident side; and

a second semiconductor section, including:
a second semiconductor substrate including a plurality of transistors; and
a second wiring layer including a third metal pad, a fourth metal pad, and a second inter-layer insulating film,
wherein the third metal pad and the fourth metal pad are disposed at a first side of the second wiring layer,

wherein the first semiconductor section and the second semiconductor section are stacked such that the first side of the first wiring layer and the first side of the second wiring layer are facing each other,
wherein the first metal pad and the third metal pad are electrically connected to each other,
wherein a portion of the pixel array region overlaps the first metal pad and the third metal pad,
wherein the second metal pad and the fourth metal pad are electrically connected to each other,
wherein a portion of the second metal pad contacts a first portion of the second inter-layer insulating film,
wherein the first wiring layer includes a fifth metal pad for external electrical connection,
wherein the second metal pad and the fourth metal pad are disposed between the fifth metal pad and the pixel array region,
wherein the first wiring layer includes a plurality of sixth metal pads overlapping corners of the fifth metal pad and electrically connected to the fifth metal pad, and
wherein the plurality of sixth metal pads extends beyond edges of the fifth metal pad and simultaneously connects with a plurality of corresponding pads provided in the second wiring layer.

2. The imaging device according to claim 1 , wherein a portion of the fourth metal pad contacts a first portion of the first inter-layer insulating film.

3. The imaging device according to claim 2 , wherein a second portion of the first inter-layer insulating film contacts a second portion of the second inter-layer insulating film, and wherein a portion of the pixel array region overlaps the second portion of the first inter-layer insulating film and the second portion of the second inter-layer insulating film.

4. The imaging device according to claim 1 , wherein the first metal pad is electrically connected to a wiring in the first wiring layer.

5. The imaging device according to claim 1 , wherein the third metal pad is electrically connected to a wiring in the second wiring layer.

6. The imaging device according to claim 1 , wherein the plurality of sixth metal pads is ring shaped.

7. The imaging device according to claim 1 , wherein the plurality of sixth metal pads includes one or more openings, and wherein the fifth metal pad completely overlaps the one or more openings.

8. An imaging device, comprising:
a first semiconductor section, including:
a photodiode;
a transfer transistor;
a first metal pad;
a second metal pad; and
a first inter-layer insulating film,
wherein the photodiode and the transfer transistor are disposed in a pixel array region,
wherein the first metal pad and the second metal pad are disposed at a first side of the first semiconductor section, and
wherein the first side of the first semiconductor section is opposite to a light incident side of the first semiconductor section; and

a second semiconductor section, including:
a plurality of transistors;
a third metal pad;
a fourth metal pad; and
a second inter-layer insulating film,
wherein the third metal pad and the fourth metal pad are disposed at a first side of the second semiconductor section,

wherein the first semiconductor section and the second semiconductor section are stacked such that the first side of the first semiconductor section and the first side of the second semiconductor section are facing each other,
wherein the first metal pad and the third metal pad are electrically connected to each other,
wherein a portion of the pixel array region overlaps the first metal pad and the third metal pad,
wherein the second metal pad and the fourth metal pad are electrically connected to each other,
wherein a portion of the second metal pad contacts a first portion of the second inter-layer insulating film,
wherein the first wiring layer includes a fifth metal pad for external electrical connection,
wherein the second metal pad and the fourth metal pad are disposed between the fifth metal pad and the pixel array region,
wherein the first wiring layer includes a plurality of sixth metal pads overlapping corners of the fifth metal pad and electrically connected to the fifth metal pad, and
wherein the plurality of sixth metal pads extends beyond edges of the fifth metal pad and simultaneously connects with a plurality of corresponding pads provided in the second wiring layer.

9. The imaging device according to claim 8 , wherein a portion of the fourth metal pad contacts a first portion of the first inter-layer insulating film.

10. The imaging device according to claim 9 , wherein a second portion of the first inter-layer insulating film contacts a second portion of the second inter-layer insulating film, wherein a portion of the pixel array region overlaps the second portion of the first inter-layer insulating film and the second portion of the second inter-layer insulating film.

11. The imaging device according to claim 8 , wherein the first metal pad is electrically connected to a wiring in the first semiconductor section.

12. The imaging device according to claim 8 , wherein the third metal pad is electrically connected to a wiring in the second semiconductor section.

Assignees

• Sony Corp

Inventors

• Kagawa Yoshihisa
• Fujii Nobutoshi
• Fukasawa Masanaga
• Kaneguchi Tokihisa
• Hagimoto Yoshiya
• Aoyagi Kenichi
• Mitsuhashi Ikue

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/792

  between multiple chips · CPC title