Method for controlling power supply voltage in semiconductor integrated circuit

US10802997B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10802997-B2
Application numberUS-201816111668-A
CountryUS
Kind codeB2
Filing dateAug 24, 2018
Priority dateJun 11, 2013
Publication dateOct 13, 2020
Grant dateOct 13, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor integrated circuit operates with a voltage supplied from a first power supply IC to transmit and receive data to and from an external memory. The semiconductor integrated circuit includes: an interface circuit operating with a voltage supplied from a second power supply IC and accessing the external memory to transmit and receive data to and from the external memory; a determination circuit which determines, based on a result of the access by the interface circuit, an AC timing specification between the external memory and the interface circuit to generate control information for controlling an output voltage of the second power supply IC in accordance with the AC timing specification; and a voltage control circuit which controls the output voltage of the second power supply IC in accordance with the control information.

First claim

Opening claim text (preview).

What is claimed is: 1. A method in a semiconductor integrated circuit including an interface circuit, a part of the semiconductor integrated circuit other than the interface circuit being supplied a voltage from a first power supply integrated circuit (IC) dynamically changing an output voltage of the first power supply IC, for controlling a voltage supplied from a second power supply IC different from the first power supply IC to the interface circuit, the method comprising steps of: (a) accessing an external memory to transmit and receive data to and from the external memory, by the interface circuit; (b) changing a control information for controlling an output voltage of the second power supply IC independently from the first power supply IC based on a result of the access done by the interface circuit; and (c) transmitting or receiving data to or from the external memory by the interface circuit with the controlled output voltage of the second power supply IC. 2. The method of claim 1 , wherein the step (b) includes determining an alternate current (AC) timing specification between the external memory and the interface circuit. 3. The method of claim 2 , wherein the step (b) includes changing the control information to indicate the output voltage of the second power supply IC be lowered if the AC timing specification is larger than a predetermined value, and the output voltage of the second power supply IC be raised if the AC timing specification is smaller than the predetermined value. 4. The method of claim 2 , the in the step (b), the control information is changed further based on a stored value of the voltage to be output by the second power supply IC, wherein the AC timing specification is associated with the value. 5. The method of claim 1 , wherein the step (a) is done in a test mode and the step (c) is done in a normal mode. 6. The method of claim 1 , wherein in the step (b), the control information is changed further based on temperature information from a temperature sensor within the semiconductor integrated circuit. 7. The method of claim 1 , wherein in the step (b), the control information is changed further based on the interface circuit's own process induced variation from a process sensor within the semiconductor integrated circuit. 8. The method of claim 1 , wherein in the step (b), the control information is changed further based on a voltage from a voltage monitor within the semiconductor integrated circuit.

Assignees

Inventors

Classifications

  • Power saving in microcontroller unit · CPC title

  • by lowering the supply or operating voltage · CPC title

  • Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

  • wherein the variable actually regulated by the final control device is AC (G05F1/625 takes precedence) · CPC title

  • Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

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What does patent US10802997B2 cover?
A semiconductor integrated circuit operates with a voltage supplied from a first power supply IC to transmit and receive data to and from an external memory. The semiconductor integrated circuit includes: an interface circuit operating with a voltage supplied from a second power supply IC and accessing the external memory to transmit and receive data to and from the external memory; a determina…
Who is the assignee on this patent?
Socionext Inc
What technology area does this patent fall under?
Primary CPC classification G06F13/1689. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Oct 13 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).