Enhanced bit flipping scheme

Patent metadata

Field	Value
Publication number	US-10802909-B2
Application number	US-201816104470-A
Country	US
Kind code	B2
Filing date	Aug 17, 2018
Priority date	Aug 17, 2018
Publication date	Oct 13, 2020
Grant date	Oct 13, 2020

Abstract

Methods, systems, and devices for operating memory cell(s) using an enhanced bit flipping scheme are described. An enhanced bit flipping scheme may include methods, systems, and devices for performing error correction of data bits in a codeword concurrently with the generation of a flip bit that indicates whether data bits in a corresponding codeword are to be flipped; for refraining from performing error correction of inversion bit(s) in the codeword; and for generating a high-reliability flip bit using multiple inversion bits. For instance, a flip bit that is even more reliable may be generated by determining whether a number of, a majority of, or all of the inversion bits indicate that the data bits are in an inverted state.

First claim

What is claimed is:

1. A method, comprising:
receiving a codeword that comprises a plurality of data bits and a plurality of inversion bits, the plurality of inversion bits indicating whether the plurality of data bits are in an inverted state, wherein each of the plurality of inversion bits has one of a first value or a second value;
performing an error correction of the plurality of data bits of the codeword to obtain a plurality of error-corrected data bits;
generating, concurrent with the error correction, a flip bit based at least in part on a quantity of the plurality of inversion bits having the first value;
transmitting the plurality of error-corrected data bits and the flip bit to a bit flipping component; and
inverting, at the bit flipping component, the plurality of error-corrected data bits based at least in part on the flip bit.

2. The method of claim 1 , further comprising:
determining whether the plurality of data bits are in the inverted state based at least in part on the quantity of the plurality of inversion bits having the first value, wherein the flip bit is generated based at least in part on determining whether the plurality of data bits are in the inverted state.

3. The method of claim 1 , further comprising:
determining that a majority of the plurality of inversion bits indicates that the plurality of data bits are in the inverted state by comparing the first value or the second value stored by each of the quantity of the plurality of inversion bits; and
determining that the plurality of data bits are in the inverted state based at least in part on determining that the majority of the plurality of inversion bits indicate that the plurality of data bits are in the inverted state.

4. The method of claim 3 , further comprising:
flipping the plurality of data bits based at least in part on determining that the plurality of data bits are in the inverted state; and
transmitting the plurality of data bits a memory buffer after the plurality of data bits are flipped.

5. The method of claim 1 , further comprising:
determining that a minority of the plurality of inversion bits indicates that the plurality of data bits are in the inverted state by comparing the first value or the second value stored by each of the quantity of the plurality of inversion bits; and
determining that the plurality of data bits are in an original state based at least in part on determining that the minority of the plurality of inversion bits indicate that the plurality of data bits are in the inverted state; and
transmitting the plurality of data bits to a memory buffer.

6. The method of claim 1 , wherein performing the error correction comprises:
generating syndrome bits for the plurality of data bits while or after generating the flip bit.

7. The method of claim 6 , further comprising:
transmitting the plurality of data bits to a bit correction component coupled with the bit flipping component; and
transmitting the syndrome bits to the bit correction component after the flip bit is transmitted to the bit flipping component.

8. The method of claim 6 , further comprising:
determining whether a data bit of the plurality of data bits is corrupted during the error correction, wherein the syndrome bits are generated based at least in part on determining whether the data bit of the plurality of data bits is corrupted.

9. The method of claim 1 , wherein a raw bit error rate (RBER) of the flip bit or a first uncorrectable bit error rate (UBER) of the flip bit is equal to or greater than a second UBER of a data bit of the plurality of data bits.

10. The method of claim 1 , wherein a section of memory comprises codewords including the codeword, each codeword of the codewords comprising a plurality of data bits and a plurality of inversion bits, the plurality of inversion bits indicating whether the plurality of data bits are in the inverted state, the method further comprising:
performing, for each codeword, an error correction operation;
determining, for each codeword and independent of the error correction of the codeword, a flip bit has one of the first value or the second value based at least in part on the plurality of inversion bits; and
transmitting, for each codeword, the flip bit to one or more bit flipping components, the one or more bit flipping components comprising the bit flipping component.

11. A method, comprising:
determining, for a codeword comprising a plurality of data bits and a plurality of inversion bits indicating whether the plurality of data bits are in an inverted state, whether a majority of the plurality of inversion bits indicates that the plurality of data bits are in the inverted state;
performing an error correction of the codeword to obtain a plurality of error-corrected data bits;
generating a flip bit based at least in part on determining whether the majority of the plurality of inversion bits indicates that the plurality of data bits are in the inverted state;
transmitting the plurality of error-corrected data bits and the flip bit to a bit flipping component; and
inverting, at the bit flipping component, the plurality of error-corrected data bits based at least in part on the flip bit.

12. The method of claim 11 , further comprising:
generating syndrome bits for the plurality of data bits based at least in part on the error correction; and
transmitting the syndrome bits, concurrent with transmitting the flip bit to the bit flipping component, to a bit correction component that is coupled with the bit flipping component.

13. The method of claim 11 , further comprising:
generating syndrome bits for the plurality of data bits based at least in part on the error correction;
transmitting the plurality of data bits to a bit correction component that is coupled with the bit flipping component; and
transmitting the syndrome bits to the bit correction component after transmitting the flip bit to the bit flipping component.

14. The method of claim 11 , wherein a first error rate associated with the flip bit is equal to or greater than a second error rate associated with the plurality of data bits.

15. An apparatus, comprising:
a data component configured to process a plurality of data bits;
a control component configured to process a plurality of control bits that comprise a plurality of inversion bits indicating whether the plurality of data bits are in an inverted state, wherein each of the plurality of inversion bits has one of a first value or a second value;
an error identification component coupled with the data component and the control component, the error identification component configured to identify errors in the plurality of data bits and perform an error correction of the plurality of data bits to obtain a plurality of error-corrected data bits;
a flip bit generator configured to determine whether the plurality of error-corrected data bits are in the inverted state based on whether a majority of the plurality of inversion bits indicates that the plurality of error-corrected data bits are in the inverted state and to generate a flip bit; and
a bit flipping component configured to flip the plurality of error-corrected data bits based at least in part on the flip bit.

16. The apparatus of claim 15 , wherein the error identification component and the flip bit generator are operated independently of one another, and wherein the plurality of control bits comprise error correction bits and redundant bits.

17. The apparatus of claim 15 , wherein the flip bit generator is included within the control component a

Assignees

• Micron Technology Inc

Inventors

• Fackenthal Richard E

Classifications

• H03M13/05

  using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits {(H03M13/2906 takes precedence)} · CPC title

• G06F11/1012 Primary

  using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• H03M13/37 Primary

  Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35 · CPC title

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title