Data dependent allocation of error correction resources

Patent metadata

Field	Value
Publication number	US-10802908-B2
Application number	US-201816051416-A
Country	US
Kind code	B2
Filing date	Jul 31, 2018
Priority date	Jul 31, 2018
Publication date	Oct 13, 2020
Grant date	Oct 13, 2020

Abstract

Various method and apparatus embodiments for data dependent error correction code (ECC) encoding are disclosed. In one embodiment, a data object may include multiple portions, with each portion having different characteristics. An ECC encoder may allocate error correction resources (e.g., parity bits) to the different portions at respectively different data rates (e.g., more error correction resources to some portions relative to other portions). Upon completion of the allocation, the data object and the associated error correction resources are forwarded to a storage medium for storage therein.

First claim

What is claimed is:

1. An apparatus comprising:
a storage medium configured to store data, the storage medium including a first region and a second region, wherein the first region provides faster access than the second region; and
a controller configured to:
allocate error correction resources at a first rate per unit of data to a first portion of a data object;
allocate error correction resources at a second rate per unit of data to a second portion of the data object, wherein the first rate is greater than the second rate, and wherein the first portion of the data object has a higher sensitivity to data corruption than the second portion; and
store the data object and the error correction resources allocated to the data object, in the storage medium such that the first portion is stored in the first region and the second portion is stored in the second region.

2. The apparatus as recited in claim 1 , wherein the error correction resources include parity bits defined according to an error correcting code (ECC).

3. The apparatus as recited in claim 1 , wherein the data object is encoded according to an encoding format that defines a first group of code tables and a second group of code tables, wherein the first portion corresponds to the first group of code tables.

4. The apparatus as recited in claim 1 , wherein the data object is encoded according to a progressive encoding format that includes a first layer that defines a baseline level of encoded information and one or more additional layers that define one or more additional levels of detail of the encoded information, wherein the first portion corresponds to one of the one or more additional layers.

5. The apparatus as recited in claim 1 , wherein the second portion of the data object is encoded based on the first portion of the data object, so that corruption of the first portion affects an ability of the second portion to be decoded.

6. The apparatus as recited in claim 1 , wherein the controller is further configured to identify that the second portion of the data object corresponds to lower priority information than the first portion of the data object based on metadata associated with the data object.

7. A controller comprising:
a host interface configured to communicate between the controller and a host device;
a storage interface configured to facilitate communications between the controller and a storage medium, the storage medium including a first region and a second region, wherein the first region provides faster access than the second region; and
data path circuitry coupled between the host interface and the storage interface, wherein the data path circuitry includes:
an error correction code (ECC) encoder configured to allocate parity bits to a data object having at least two different data types including a first portion of a first data type and a second portion of a second data type, wherein the ECC encoder is further configured to identify that the second portion of the data object is less sensitive to corruption than the first portion of the data object, wherein the ECC encoder is further configured to allocate parity bits at a first rate per unit of data to the data of the first data type and allocate parity bits at a second rate per unit of data to the data of the second data type, the first rate being greater than the second rate;

wherein the storage interface is further configured to convey the data object, and the allocated parity bits, to the storage medium; and
wherein the controller is further configured to cause the storage medium to store the first portion in the first region and to store the second portion in the second region.

8. The controller as recited in claim 7 , further comprising an ECC decoder coupled to the storage interface, wherein the ECC decoder is configured to determine if any errors are present in data received by the controller from the storage medium based at least in part on information stored in a plurality of log likelihood ratio (LLR) tables, wherein each of the LLR tables corresponds to a unique data type and includes a plurality of entries, each of the plurality of entries of a given LLR table including reliability scores for a plurality of voltage ranges for individual bits of data read from the storage medium.

9. The controller as recited in claim 7 , further comprising an ECC decoder coupled to the storage interface, the ECC decoder configured to determine if any errors are present in data received by the controller from the storage medium, wherein the ECC decoder includes a low density parity code (LDPC) engine configured to operate in one of a plurality of different modes depending on a region of data for which a presence of errors is to be determined.

10. The controller as recited in claim 9 , wherein the LDPC engine is further configured to operate in a first power mode during error checking of a first region of data, and further configured to operate in a second power mode during error checking of a second region of data.

11. The controller as recited in claim 9 , wherein the LDPC engine is further configured to operate in accordance with one or more tuning parameters, wherein the one or more tuning parameters includes one or more of the following:
a soft bit delta;
a read threshold voltage.

12. A data storage device comprising the controller as recited in claim 7 .

13. A method comprising:
receiving, by a controller, a data object;
determining a format of the data object using the controller;
allocating parity bits to the data object based on the format, wherein allocating parity bits comprises allocating a first number of parity bits per unit of data to a first portion of the data object and a second number of parity bits per unit of data to a second portion of the data object, wherein the first number of parity bits per unit of data is greater than the second number of parity bits per unit of data; and
storing the data object, including the parity bits, in a storage device, wherein the first portion is stored in a first region of a storage medium of the storage device and the second portion is stored in a second region of the storage medium, and wherein the first region of the storage medium provides faster access than the second region.

14. The method as recited in claim 13 , further comprising:
the controller reading the data object from the storage device;
the controller determining if any errors are present in the first portion using the parity bits allocated to the first portion;
the controller determining if any errors are present in the second portion using the parity bits allocated to the second portion; and
correcting any errors determined to be present in either of the first and second portions.

15. The method as recited in claim 13 , wherein allocating parity bits to the first and second portions comprises allocating different numbers of parity bits based on unique characteristics of each of the first and second portions.

16. A system comprising:
a controller configured to:
receive a data file;
determine a file format of the data file;
determine respective characteristics of each of first and second portions of the data file; and
allocate error correction information, using an error correction code (ECC) encoder implemented in the controller, at a first rate per unit of data to the first portion and at a second rate per unit of data to the second portion, wherein the first rate is greater than the second rate; and

a storage device including a storage medium, the storage medium including a first region and a second region, wherein the first

Assignees

• Western Digital Tech Inc

Inventors

• Pele Ofir
• Navon Ariel
• Bazarsky Alex

Classifications

• G06F11/0781

  Error filtering or prioritizing based on a policy defined by the user or on a policy defined by a hardware/software module, e.g. according to a severity level · CPC title

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title

• H03M13/1114

  Merged schedule message passing algorithm with storage of sums of check-to-bit node messages or sums of bit-to-check node messages, e.g. in order to increase the memory efficiency · CPC title

• G06F11/10 Primary

  Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's · CPC title