Apparatus and method for measuring current source mismatches in current-steering DAC by re-using R2R network

Patent metadata

Field	Value
Publication number	US-10797720-B2
Application number	US-201916367712-A
Country	US
Kind code	B2
Filing date	Mar 28, 2019
Priority date	Sep 21, 2018
Publication date	Oct 6, 2020
Grant date	Oct 6, 2020

Abstract

A current digital-to-analog converter includes a binary current-generating section configured to generate a binary-weighted current based on a first set of control signals; a unary current-generating section configured to generate a unary-weighted current based on a second set of control signals; and a current combining circuit configured to add or subtract a reference current and a current generated by a current source of the unary current-generating section using the binary-weighted current.

First claim

What is claimed:

1. An apparatus for measuring current mismatch, comprising:
a current digital-to-analog converter (DAC) configured to convert an input digital signal into an output analog current, comprising:
a first current-generating section configured to generate a first current based on a first set of control signals;
a second current-generating section configured to generate a second current based on a second set of control signals, wherein the first and second currents are summed to generate the output analog current;
a current combining circuit configured to add or subtract a reference current and a current generated by a current source of the second current-generating section using the first current; and
a comparator coupled to the current combining circuit and to the first current-generating section.

2. The apparatus of claim 1 , wherein the first current-generating section comprises an R2R resistor network, wherein the first current is generated at a node of the R2R resistor network.

3. The apparatus of claim 2 , wherein the current combining circuit comprises a scaling device configured to scale the first current, wherein the current combining circuit is configured to add or subtract the reference current and the current generated by the current source using the scaled first current.

4. The apparatus of claim 3 , wherein the scaling device comprises a resistor.

5. The apparatus of claim 3 , wherein the comparator is configured to compare an output current or output voltage generated by the current combining circuit with a reference voltage.

6. The apparatus of claim 5 , wherein the comparator includes a first input coupled to the current combining circuit and a second input configured to receive the reference voltage and coupled to a resistor.

7. The apparatus of claim 1 , wherein the first current-generating section comprises:
a set of current sources configured to generate a set of currents; and
an R2R resistor network configured to generate the first current based on one or more of the set of current sources.

8. The apparatus of claim 7 , wherein the current combining circuit comprises a first resistor configured to scale the first current, wherein the current combining circuit is configured to add or subtract the reference current and the current generated by the current source using the scaled first current.

9. The apparatus of claim 8 , wherein the comparator includes a first input coupled to the current combining circuit and a second input coupled to a second resistor.

10. The apparatus of claim 1 , wherein the first current comprises a binary-weighted current, and wherein the second current comprises unary-weighted current.

11. The apparatus of claim 1 , wherein the first current-generating section and the second current-generating section are single-ended or differential current-generating sections, respectively.

12. The apparatus of claim 1 , wherein the current combining circuit comprises a current summer configured to generate a third current based on a sum of the first current with the reference current.

13. The apparatus of claim 12 , wherein the current combining circuit further comprises a current subtractor configured to generate a fourth current based on a difference between the current from the current source and the third current.

14. The apparatus of claim 13 , wherein the current subtractor comprises a current mirror including a first input configured to receive the current from the current source and a second input configured to receive the third current.

15. The apparatus of claim 13 , wherein the current combining circuit further comprises a current comparator configured to generate a signal based on a comparison of the fourth current with a threshold.

16. The apparatus of claim 13 , wherein the current combining circuit further comprises a controller configured to generate the first set of control signals to adjust the first current to decrease the fourth current to substantially nil.

17. The apparatus of claim 16 , wherein a value of the first set of control signals when the fourth current is substantially nil provides an indication of a mismatch between the reference current and the current generated by the current source.

18. The apparatus of claim 1 , wherein the current combining circuit is configured to measure a current mismatch between the reference current and another current generated by another current source of the first current-generating section.

19. The apparatus of claim 1 , wherein the second current-generating section comprises a set of current sources including the current source, and further comprising a controller configured to adjust the current source based on a current mismatch between the current generated by the current source and the reference current.

20. The apparatus of claim 1 , wherein the first current-generating section comprises an R 2 R network, wherein the comparator includes an input coupled to a node within the R 2 R network.

21. The apparatus of claim 1 , further comprising a buffer, wherein the first current-generating section comprises an R 2 R network, and wherein the comparator includes an input coupled to a node within the R 2 R network via the buffer.

22. The apparatus of claim 1 , wherein the first current-generating section comprises an R 2 R resistor network, wherein the first current is generated at a node of the R 2 R resistor network, wherein the comparator includes a first input coupled to the current combining circuit and a second input configured to receive a reference voltage and coupled to a resistor.

23. The apparatus of claim 1 , wherein:
the first current-generating section is configured to generate the first current based on the first set of control signals in a first mode or a second mode;
the second current-generating section is configured to generate the second current based on the second set of control signals in the first mode or the second mode, wherein the first and second currents are summed to generate the output analog current in the first mode; and
the current combining circuit configured to add or subtract a reference current and the current generated by the current source of the second current-generating section using the first current in the second mode.

24. A digital-to-analog converter circuit for converting an input digital signal to an output analog current, comprising:
a first section configured to generate a first, comprising:
a first set of current sources configured to generate a first set of one or more currents, respectively; and
one or more resistive networks configured to generate the first current based on the first set of one or more currents;

a second section configured to generate a second current, wherein the second section comprises a second set of current sources, wherein the first and second currents are summed to generate the output analog current in response to the input digital signal; and
a measurement circuit operably coupled to the first section and the second.

25. The digital-to-analog converter circuit of claim 24 , wherein the measurement circuit is configured to output a signal indicative of an amount of current mismatch between a reference current and the second current from at least one of the second set of current sources.

26. The digital-to-analog converter circuit of claim 24 , wherein the first section is a binary current-generating sectio

Assignees

• Qualcomm Inc

Inventors

• Sung Eunyung
• Saputra Nitz
• Sedighi Behnam
• Swaminathan Ashok
• Ji Honghao
• Mehdizad Taleie Shahin
• Seo Dongwon

Classifications

• H03M1/785

  using resistors, i.e. R-2R ladders · CPC title

• H03M1/687

  Segmented, i.e. the more significant bit converter being of the unary decoded type and the less significant bit converter being of the binary weighted type · CPC title

• H03M1/745 Primary

  with weighted currents · CPC title

• H03M1/747

  with equal currents which are switched by unary decoded digital signals · CPC title