Common signal attenuation circuit and ramp signal generator using the same

Patent metadata

Field	Value
Publication number	US-10797682-B2
Application number	US-201715680848-A
Country	US
Kind code	B2
Filing date	Aug 18, 2017
Priority date	Dec 26, 2016
Publication date	Oct 6, 2020
Grant date	Oct 6, 2020

Abstract

A common signal attenuation circuit may include a sensing block suitable for sensing differential signals to generate sensed differential signals; a common signal generation block suitable for generating an common signal having a common voltage noise by combining the sensed differential signals; and an attenuation block suitable for adjusting the common voltage noise in the original common signal by combining the common signal having the adjusted common voltage noise to the differential signals.

First claim

What is claimed is:

1. A common signal attenuation circuit comprising:
a sensing block suitable for sensing differential signals;
a common signal generation block suitable for summing the differential signals, which are sensed by the sensing block, and generating a common signal having a common voltage noise, wherein the differential signals include first and second differential signals having opposite phases to each other, and differential components of the first and second differential signals are removed and the common voltage noise of the first and second differential signals is doubled in the opposite phases; and
an attenuation block suitable for adjusting the common voltage noise included in the common signal by combining the common signal having the adjusted common voltage noise to the differential signals,
wherein the differential signals are of current-type, and
wherein the common signal generation block comprises:
a third PMOS transistor suitable for transmitting the first current-type differential signal sensed by the sensing block;
a fourth PMOS transistor suitable for transmitting the second current-type differential signal sensed by the sensing block; and
a first NMOS transistor suitable for generating the common signal having a common voltage noise by combining the first current-type differential signal and the second current-type differential signal with each other.

2. The common signal attenuation circuit of claim 1 , further comprising a distortion reduction block suitable for reducing distortion of the differential signals and providing the distortion-reduced differential signals to the sensing block.

3. The common signal attenuation circuit of claim 2 ,
wherein the distortion attenuation block comprises:
a first impedance unit suitable for reducing distortion of the first differential signal and providing the distortion-reduced first differential signal to the sensing block; and
a second impedance unit suitable for reducing distortion of the second differential signal and providing the distortion-reduced second differential signal to the sensing block.

4. The common signal attenuation circuit of claim 2 , wherein the distortion reduction block includes a buffer.

5. The common signal attenuation circuit of claim 1 , wherein the differential signals include current-type differential signals.

6. The common signal attenuation circuit of claim 1 , wherein the attenuation block amplifies or attenuates the common voltage noise in the common signal and combines the amplified or attenuated common signal to the differential signals thereby attenuating the common voltage noise of the differential signals.

7. The common signal attenuation circuit of claim 1 ,
wherein the sensing block comprises:
a first PMOS transistor suitable for sensing, in a current form, the first differential signal; and
a second PMOS transistor suitable for sensing, in a current form, the second differential signal.

8. The common signal attenuation circuit of claim 1 ,
wherein the attenuation block comprises:
a second NMOS transistor suitable for amplifying or attenuating and transmitting the common signal having the common voltage noise generated from the common signal generation block;
a fifth PMOS transistor suitable for transmitting the opposite-phase common signal from the second NMOS transistor;
a sixth PMOS transistor suitable for amplifying or attenuating the common voltage noise in the common signal provided from the fifth PMOS transistor to generate a common signal having the amplified or attenuated common voltage noise and combining the common signal to the first differential signal so that the common voltage noise included in the first differential signal is attenuated; and
a seventh PMOS transistor suitable for amplifying or attenuating the opposite-phase common signal provided from the fifth PMOS transistor to generate the common signal having the amplified or attenuated common voltage noise and combining the common signal to the second differential signal so that the common voltage noise included in the second differential signal is attenuated.

9. A ramp signal generator comprising:
a ramp signal generation block suitable for generating two ramp signals having opposite signal phases and including a common voltage nose;
a common signal attenuation circuit suitable for summing the two ramp signals, generating a common signal having the common voltage noise from the ramp signals and attenuating the common voltage noise in the common signal based on the two ramp signals; and
a resistive load block suitable for converting the ramp signals including the attenuated common voltage noise into voltage-type ramp signals,
wherein the ramp signals include first and second ramp signals having opposite phases to each other, and
wherein differential components of the first and second ramp signals are removed and the common voltage noise of the first and second ramp signals is doubled in the opposite phases,
wherein the common signal attenuation circuit comprises:
a sensing block suitable for sensing the ramp signals;
a common signal generation block suitable for summing the ramp signals sensed by the sensing block with each other and generating the common signal having the common voltage noise; and
an attenuation block suitable for attenuating the common voltage noise by combining the common signal to the ramp signals,
wherein the ramp signals are of current-type, and
wherein the common signal generation block comprises:
a third PMOS transistor suitable for transmitting the first current-typed ramp signal sensed by the sensing block;
a fourth PMOS transistor suitable for transmitting the second current-typed ramp signal sensed by the sensing block; and
a first NMOS transistor suitable for generating the common signal having the common voltage noise by combining the first current-typed ramp signal and the second current-typed ramp signal with each other.

10. The ramp signal generator of claim 9 , further comprising a distortion reduction block suitable for reducing distortion of the ramp signals and providing the distortion-reduced ramp signals to the sensing block.

11. The ramp signal generator of claim 10 ,
wherein the distortion attenuation block comprises:
a first impedance unit suitable for reducing distortion of the first ramp signal and providing the distortion-reduced first ramp signal to the sensing block; and
a second impedance unit suitable for reducing distortion of the second ramp signal and providing the distortion-reduced second ramp signal to the sensing block.

12. The ramp signal generator of claim 9 , wherein the ramp signals are of current-type.

13. The ramp signal generator of claim 9 , wherein the attenuation block amplifies or attenuates the opposite-phase common signal and combines the amplified or attenuated opposite-phase common signal to the ramp signals thereby attenuating the common signal of the ramp signals.

14. The ramp signal generator of claim 9 , wherein the sensing block senses a ramp signal in a current form.

15. The ramp signal generator of claim 9 ,
wherein the sensing block comprises:
a first PMOS transistor suitable for sensing, in a current form, the first ramp signal; and
a second PMOS transistor suitable for sensing, in a current form, the second ramp signal.

16. The ramp signal generator of claim 9 ,
wherein the ramp signals are of current-type, and
wherein the attenuation block comprises:
a second NMOS transistor suitable for amplifying or attenuating the common voltage noise and transmitting the common signal havi

Assignees

• Sk Hynix Inc

Inventors

• Yun Gun-Hee
• PARK Hyun-Mook

Classifications

• H03K3/013 Primary

  Modifications of generator to prevent operation by noise or interference · CPC title

• H03K5/003 Primary

  Changing the DC level (reinsertion of DC component of a television signal H04N5/16) · CPC title

• H03K4/48

  using as active elements semiconductor devices (H03K4/787 - H03K4/84 take precedence) · CPC title

• H03K4/90

  Linearisation of ramp (modifying slopes of pulses H03K6/04; scanning distortion correction for television receivers H04N3/23); Synchronisation of pulses · CPC title

• H03H11/245 Primary

  using field-effect transistor · CPC title