Three-terminal optoelectronic component with improved matching of electric field and photocurrent density

Patent metadata

Field	Value
Publication number	US-10797194-B2
Application number	US-201916283224-A
Country	US
Kind code	B2
Filing date	Feb 22, 2019
Priority date	Feb 22, 2019
Publication date	Oct 6, 2020
Grant date	Oct 6, 2020

Abstract

A three-terminal avalanche photodiode provides a first controllable voltage drop across a light absorbing region and a second, independently controllable, voltage drop across a photocurrent amplifying region. The compositions of the absorbing region and the amplifying region may be optimized independently of each other. In the amplifying region, p-doped and n-doped structures are offset from each other both horizontally and vertically. Directly applying a voltage across a controlled region of the photocurrent path increases avalanche gain by shaping the electric field to overlap the photocurrent density. The resulting high-gain, low-bias avalanche photodiodes may be fabricated in integrated optical circuits using commercial CMOS processes, operated by power supplies common to mature computer architecture, and used for optical interconnects, light sensing, and other applications.

First claim

What is claimed is:

1. An avalanche photodiode comprising:
a layer of an amplifying material disposed over a substrate;
an n-doped region in the amplifying material;
a first terminal coupled to the n-doped region;
a p-doped region in the amplifying material;
a second terminal coupled to the p-doped region;
an absorbing region comprising a layer of an absorbing material disposed over the layer of the amplifying material; and
a third terminal coupled to the layer of absorbing material; and
a p-doped contact region between the absorbing region and the third terminal;
wherein the n-doped region and the p-doped region are separated both horizontally and vertically by an interstice of undoped amplifying material.

2. The avalanche photodiode of claim 1 , wherein a top surface of the p-doped region is at a greater height above the substrate than a top surface of the n-doped region.

3. The avalanche photodiode of claim 1 , wherein both a top surface and a bottom surface of the p-doped region are at a greater height above the substrate than a top surface of the n-doped region.

4. The avalanche photodiode of claim 1 , wherein the substrate comprises a silicon-on-insulator wafer.

5. The avalanche photodiode of claim 1 , wherein the interstice between the p-doped region and the n-doped region is 100-500 nanometers wide.

6. The avalanche photodiode of claim 1 , wherein the amplifying material comprises silicon, and the absorbing material comprises germanium.

7. A computing device comprising:
an avalanche photodiode, wherein the avalanche photodiode is incorporated in an integrated optical module, wherein the integrated optical module comprises an internal light source; and
a first electronic module to receive a signal from the avalanche photodiode;
wherein
an absorbing region of the avalanche photodiode is to absorb light and emit a corresponding photocurrent;
an electric field in an undoped interstice of the avalanche photodiode between a p-doped region and an n-doped region is to amplify the photocurrent; and
a distance from the absorbing region to the n-doped region is greater than a distance from the absorbing region to the p-doped region.

8. The computing device of claim 7 , wherein the first electronic module comprises at least one of an input/output interface, a processor, a data store, a dynamic memory, and a communications link.

9. The computing device of claim 7 , wherein the avalanche photodiode is to directly sense light from an external source.

10. The computing device of claim 7 , wherein the integrated optical module comprises at least one of an input/output interface, a processor, a data store, a dynamic memory, and a communications link.

11. The computing device of claim 7 , further comprising a second electronic module to control the internal light source.

12. The computing device of claim 11 , wherein the avalanche photodiode is to receive light from the internal light source, and the signal corresponds to a characteristic of the light.

13. A method for fabricating an optoelectronic component, the method comprising:
n-doping a semiconductor to form a first contact and an n-doped region;
p-doping the semiconductor to form a second contact and a p-doped region above and beside the n-doped region, leaving an undoped interstice between the p-doped region and the n-doped region;
forming an absorbing region over the p-doped region and the n-doped region;
p-doping the absorbing region to form a third contact; and
forming connections to the first contact, the second contact, and the third contact.

14. The method of claim 13 , wherein the semiconductor comprises a native silicon layer of a silicon-on-insulator substrate.

15. The method of claim 13 , wherein the p-doping of the semiconductor further comprises forming at least one additional p-doped region, and the n-doping of the semiconductor further comprises forming at least one additional n-doped region.

16. The method of claim 13 , wherein the forming of connections comprises forming a via through a layer of semiconductor overlying at least one of the first contact, the second contact, or the third contact.

17. The method of claim 13 , further comprising removing overlying semiconductor material from at least one of the first contact, the second contact, or the third contact before the forming of the connections.

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Zeng Xiaoge
• Huang Zhihong
• Liang Di

Classifications

• H10W90/00

  Package configurations · CPC title

• H10F77/959

  for devices working in avalanche mode · CPC title

• H10F77/206 Primary

  for devices having potential barriers · CPC title

• H10F71/121

  The active layers comprising only Group IV materials · CPC title

• H10F30/2255

  in which the active layers form heterostructures, e.g. SAM structures · CPC title