Vector friendly instruction format and execution thereof

Patent metadata

Field	Value
Publication number	US-10795680-B2
Application number	US-201916289506-A
Country	US
Kind code	B2
Filing date	Feb 28, 2019
Priority date	Apr 1, 2011
Publication date	Oct 6, 2020
Grant date	Oct 6, 2020

Abstract

A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

First claim

What is claimed is:

1. A computing apparatus comprising:
a processor configured to execute an instruction set, wherein the instruction set includes a first instruction format, wherein the first instruction format has a plurality of fields including a class field, an alpha field, and a beta field, wherein the first instruction format supports different augmentation operations through placement of different values in the alpha field and the beta field, wherein only one of the different values may be placed in each of the alpha field and the beta field on each occurrence of an instruction in the first instruction format in instruction streams, the processor including,
a decode unit configured to decode the occurrences of the instructions in the first instruction format with the class field's content specifying a first class as follows:
distinguish, for each of the occurrences that does not specify memory access, whether to augment with a round type operation or not based on the alpha field's content in that occurrence, wherein the beta field is interpreted as a suppress all floating point exceptions (SAE) field and a round operation field when the alpha field's content indicates the round type operation;
distinguish, for each of the occurrences that does not specify memory access and that does specify the round type operation through the alpha field's content, whether floating point exceptions will be suppressed or not based on the SAE field's content in that occurrence; and
distinguish, for each of the occurrences that does not specify memory access and that does specify the round type operation through the alpha field's content, which one of a plurality of round operations to apply based on the round operation field's content in that occurrence.

2. The computing apparatus of claim 1 , wherein the plurality of round operations includes round to nearest, round down, round up, and round toward zero.

3. The computing apparatus of claim 1 , wherein the decode unit is also configured to decode the occurrences of the instructions in the first instruction format with the class field's content specifying a second class as follows:
interpret, for each of the occurrences that does not specify memory access, the beta field as including an RL field;
distinguish, for each of the occurrences that does not specify memory access, whether to augment with a round type operation or with a vector length type operation based on the RL field's content in that occurrence, wherein a remainder of the beta field is interpreted as a round operation field when the RL field's content indicates the round type operation, and wherein the remainder of the beta field is instead interpreted as a vector length field when the RL field's content indicates the vector length type operation; and
distinguish, for each of the occurrences that does not specify memory access and that does specify the round type operation through the RL field's content, which one of the plurality of round operations to apply based on the beta field's content and its interpretation as the round operation field in that occurrence.

4. The computing apparatus of claim 3 , wherein, for each of the occurrences that does not specify memory access and that does specify the round type operation through the RL field's content, floating point exceptions are suppressed.

5. The computing apparatus of any one of claim 3 or 4 , wherein the decode unit is also configured to decode the occurrences of the instructions in the first instruction format with the class field's content specifying the second class as follows:
distinguish, for each of the occurrences that does not specify memory access and that does specify the vector length type operation through the RL field's content, which one of a plurality of vector lengths to use based on the beta field's content and its interpretation as the vector length field in that occurrence.

6. The computing apparatus of claim 5 , wherein the plurality of vector lengths includes 128, 256, and 512 bits.

7. The computing apparatus of claim 1 , wherein length of vector operated on by the first class is 512 bits.

8. The computing apparatus of claim 1 , wherein the first instruction format further includes a data element width field, wherein the first instruction format supports through different values in the data element width field the specification of different data element widths.

9. The computing apparatus of claim 8 , wherein the first instruction format supports through different values in the data element width field the specification of a 32 bit and a 64 bit data element width for the first class.

Assignees

• Intel Corp

Inventors

• Valentine Robert C
• San Adrian Jesus Corbal
• Sans Roger Espasa
• Cavin Robert D
• Toll Bret L
• Duran Santiago Galan
• Wiedemeier Jeffrey G
• Samudrala Sridhar
• Girkar Milind Baburao
• Grochowski Edward Thomas
• Hall Jonathan Cannon
• Bradford Dennis R
• Ould-Ahmed-Vall Elmoustapha
• Abel James C
• Charney Mark
• Abraham Seth
• Sair Suleyman
• Forsyth Andrew Thomas
• Wu Lisa
• Yount Charles

Classifications

• H10D84/8311

  the IGFETs characterised by having different channel structures · CPC title

• H10D48/30

  Devices controlled by electric currents or voltages · CPC title

• H10D64/018

  Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/611

  having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733) · CPC title