Display device including touch sensor

US10795473B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10795473-B2
Application numberUS-201816155632-A
CountryUS
Kind codeB2
Filing dateOct 9, 2018
Priority dateDec 29, 2017
Publication dateOct 6, 2020
Grant dateOct 6, 2020

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Provided is a display device including a level shifter generating an output clock swinging between a first voltage and a third voltage during a display period and swinging between a second voltage and the third voltage during a touch sensing period. Waveform distortion of a no-load alternating current (AC) signal may be prevented without eliminating a stabilizing capacitor of the level shifter, and thus, sensing sensitivity may be increased by reducing noise of a touch sensor signal.

First claim

Opening claim text (preview).

What is claimed is: 1. A display device comprising: a display panel including a plurality of data lines and a plurality of gate lines intersecting the plurality of data lines, a plurality of pixels arranged in a matrix form, and a plurality of touch sensors connected to the plurality of pixels; a power supply unit generating a first voltage, a second voltage that is less than the first voltage, and a third voltage that is less than the first voltage and greater than the second voltage; a control signal generating unit generating a synchronization signal defining a display period during which the display panel displays an image and a touch sensing period during which touch of the display panel is sensed, and an input clock defining a gate pulse period during the display period and defining a pulse period of an alternating current (AC) signal during the touch sensing period; a level shifter receiving the synchronization signal, the input clock, the first voltage, the second voltage, and the third voltage and generating an output clock swinging between the first voltage and the second voltage during the display period, the output clock swinging between the second voltage and the third voltage during the touch sensing period; and a gate driver supplying a gate pulse swinging between the first voltage and the second voltage to the plurality of gate lines during the display period and supplying the AC signal swinging between the third voltage and the second voltage to the plurality of gate lines during the touch sensing period. 2. The display device of claim 1 , wherein the gate driver includes a shift register that shifts the output clock received from the level shifter. 3. The display device of claim 2 , wherein the second voltage is supplied to the level shifter through a low potential power supply line between the power supply unit and the level shifter, and the display device further comprising: a stabilizing capacitor connected to the low potential power supply line. 4. The display device of claim 3 , wherein the level shifter includes: a first transistor turned on responsive to the input clock being at a first logic voltage during the display period and charge a voltage of an output node of the level shifter to the first voltage during the display period, and the first transistor turned off during the touch sensing period; a second transistor turned on responsive to the input clock being at a second logic level that is less than the first logic level during the display period and the touch sensing period, the second transistor discharging the voltage of the output node to the second voltage; and a third transistor that is off during the display period and turned on responsive to the input clock being at the first logic voltage during the touch sensing period, the third transistor charging the output node to the third voltage. 5. The display device of claim 4 , further comprising: a fourth transistor turned on responsive to the input clock being at the first logic voltage during the display period; a fifth transistor turned on responsive to the input clock being at the first logic voltage during the display period; a sixth transistor turned on during the display period and turned off during the touch sensing period; a seventh transistor turned off during the display period and turned on during the touch sensing period; and an eighth transistor turned off during the display period and turned on during the touch sensing period, the eighth transistor supplying the input clock to a gate electrode of the third transistor. 6. The display device of claim 1 , wherein the level shifter includes: a first transistor turned on during the gate pulse period of the display period in response to an output signal from a first logic circuit, the first transistor charging a voltage of an output node of the level shifter to the first voltage; a second transistor turned on during a second voltage period of the display period excluding the gate pulse period and a second voltage period of the touch sensing period excluding the pulse period of the AC signal in response to an output signal from a second logic circuit, the second transistor discharging the voltage of the output node to the second voltage; and a third transistor turned on during the pulse period of the AC signal within the touch sensing period in response to an output signal from a third logic circuit, the third transistor charging the output node to the third voltage. 7. The display device of claim 6 , wherein the first logic circuit includes: a first AND gate outputting a result of an AND operation of the synchronization signal and the input clock; and a first inverter inverting an output signal from the first AND gate and applying the inverted output signal to a gate electrode of the first transistor. 8. The display device of claim 7 , wherein the third logic circuit includes: a second inverter inverting the synchronization signal; and a second AND gate applying a result of an AND operation of the inverted synchronization signal and the input clock to a gate of the third transistor. 9. The display device of claim 8 , wherein the second logic circuit includes: a third inverter inverting the output signal from the second AND gate; and a third AND gate applying an AND operation to the inverted output signal generated by the first inverter and the output signal from the third inverter to a gate electrode of the second transistor. 10. A display device comprising: a display panel including a plurality of data lines and a plurality of gate lines intersecting the plurality of data lines, a plurality of pixels arranged in a matrix form, and a plurality of touch sensors connected to the plurality of pixels; a power supply unit generating a first voltage, a second voltage that is less than the first voltage, and a third voltage that is less than the first voltage and greater than the second voltage; a control signal generating unit generating a synchronization signal defining a display period during which the display panel display an image and a touch sensing period during which touch of the display panel is sensed, an input clock defining a gate pulse period during the display period and defining a pulse period of an alternating current (AC) signal during the touch sensing period, and a pulse width modulation (PWM) signal defining a pulse period of the AC signal during the touch sensing period; a level shifter receiving the synchronization signal, the input clock, the first voltage, the second voltage, and the third voltage and generating an output clock swinging between the first voltage and the second voltage during the display period and the output clock swinging between the second voltage and the third voltage during the touch sensing period; and a gate driver supplying a gate pulse swinging between the first voltage and the second voltage to the plurality of gate lines during the display period and supplying the AC signal swinging between the third voltage and the second voltage to the plurality of gate lines during the touch sensing period. 11. The display device of claim 10 , wherein the gate driver includes a shift register that shifts a signal input from the level shifter. 12. The display device of claim 11 , wherein the second voltage is supplied to the level shifter through a low potential power supply line between the power supply unit and the level shifter, and the display device further comprising: a stabilizing capacitor connected to the low potential power supply line. 13. The display device of claim 12 , wherein the level shifter includes: a first transistor turned on du

Assignees

Inventors

Classifications

  • G06F3/0418Primary

    for error correction or compensation, e.g. based on parallax, calibration or alignment · CPC title

  • G06F3/0412Primary

    Digitisers structurally integrated in a display · CPC title

  • by capacitive means · CPC title

  • Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors · CPC title

  • Aspects of interface with display user · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10795473B2 cover?
Provided is a display device including a level shifter generating an output clock swinging between a first voltage and a third voltage during a display period and swinging between a second voltage and the third voltage during a touch sensing period. Waveform distortion of a no-load alternating current (AC) signal may be prevented without eliminating a stabilizing capacitor of the level shifter,…
Who is the assignee on this patent?
Lg Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification G06F3/0418. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Oct 06 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).