Array substrate with diffuse reflection layer, method for manufacturing the same, and display device comprising the same

Patent metadata

Field	Value
Publication number	US-10795228-B2
Application number	US-201816121968-A
Country	US
Kind code	B2
Filing date	Sep 5, 2018
Priority date	Sep 6, 2017
Publication date	Oct 6, 2020
Grant date	Oct 6, 2020

Abstract

The present disclosure provides an array substrate, a method for manufacturing the same, and a display device. The array substrate includes a base substrate, and gate lines and data lines arranged on the base substrate to define a plurality of pixel regions, and a diffuse reflection layer arranged in the plurality of pixel regions, in which a surface of the diffuse reflection layer facing a light emitting side of the array substrate is uneven.

First claim

What is claimed is:

1. An array substrate, comprising a base substrate, a buffer layer, an active layer, a gate insulating layer, a gate metal layer, an interlayer dielectric layer, a source/drain metal layer, gate lines and data lines arranged on the base substrate to define a plurality of pixel regions, and a diffuse reflection layer arranged in the plurality of pixel regions and in direct contact with the base substrate,
wherein a surface of the diffuse reflection layer facing a light emitting side of the array substrate is uneven, and the diffuse reflection layer is made entirely of one material,
wherein in each of the plurality of pixel regions, the diffuse reflection layer is arranged in an entire pixel region other than a region where a channel of the active layer locates, and
wherein a gap for passing through backlight incident from the base substrate exists between the diffuse reflection layer and the gate line and between the diffuse reflection layer and the data line, or the diffuse reflection layer has a gap for passing through backlight incident from the base substrate.

2. The array substrate of claim 1 , further comprising a light shielding layer for sheltering a thin film transistor of the array substrate from backlight.

3. The array substrate of claim 2 , wherein the diffuse reflection layer and the light shielding layer are arranged on a same layer and made of a same material.

4. The array substrate of claim 1 , wherein an orthogonal projection of the diffuse reflection layer onto the base substrate at least partially overlaps an orthogonal projection of a corresponding one of the plurality of pixel regions onto the base substrate.

5. The array substrate of claim 4 , wherein the array substrate is an array substrate of a liquid crystal display device.

6. The array substrate of claim 1 , further comprising an insulating layer arranged on the base substrate, wherein the insulating layer is arranged on a side of the diffuse reflection layer proximate to the base substrate, and a surface of the insulating layer facing a side of the diffuse reflection layer is uneven.

7. The array substrate of claim 1 , wherein a material of the diffuse reflection layer comprises at least one of Ag, Au, Mo, Al, and Cu.

8. The array substrate of claim 1 , wherein the diffuse reflection layer comprises at least one of a plate-type structure, a strip-type structure, and a block-type structure comprising blocks arranged in a matrix form.

9. A display device, comprising the array substrate of claim 1 .

10. The display device of claim 9 , wherein the array substrate further comprises a light shielding layer for sheltering a thin film transistor of the array substrate from backlight, and the diffuse reflection layer and the light shielding layer are arranged on a same layer and made of a same material.

11. The display device of claim 9 , wherein the array substrate further comprises an insulating layer arranged on the base substrate, the insulating layer is arranged on a side of the diffuse reflection layer proximate to the base substrate, and a surface of the insulating layer facing a side of the diffuse reflection layer is uneven.

12. A method for manufacturing an array substrate, wherein the array substrate comprises a base substrate, a buffer layer, an active layer, a gate insulating layer, a gate metal layer, an interlayer dielectric layer, a source/drain metal layer, gate lines and data lines arranged on the base substrate to define a plurality of pixel regions, and a diffuse reflection layer arranged in the plurality of pixel regions and in direct contact with the base substrate, wherein a surface of the diffuse reflection layer facing a light emitting side of the array substrate is uneven, and the diffuse reflection layer is made entirely of one material,
the method comprising:
forming the diffuse reflection layer in the plurality of pixel regions, wherein the surface of the diffuse reflection layer facing the light emitting side of the array substrate is uneven; and
sequentially forming the buffer layer, the active layer, the gate insulating layer, the gate metal layer, the interlayer dielectric layer and the source/drain metal layer,
wherein the forming the diffuse reflection layer in the plurality of pixel regions comprises:
forming a metal film layer;
forming a photoresist layer on the metal film layer;
exposing and developing the photoresist layer, to form a photoresist layer pattern, wherein the photoresist layer pattern comprises at least a first pattern region corresponding to a region where the diffuse reflection layer is arranged;
removing the metal film layer not covered by the photoresist layer pattern, to form a metal film layer pattern;
bombarding the photoresist layer pattern through a plasma process to ash the photoresist layer pattern, and continuing to bombard the metal film layer pattern so as to provide the metal film layer pattern with an uneven surface, wherein the metal film layer pattern comprises a pattern of the diffuse reflection layer; and
stripping off the remaining photoresist layer.

13. The method of claim 12 , wherein
prior to forming the diffuse reflection layer in the plurality of pixel regions, the method further comprises:
forming an insulating layer; and
bombarding the insulating layer through a plasma process, to form an insulating layer having an uneven surface,
wherein the forming the diffuse reflection layer in the plurality of pixel regions comprises:
forming a metal film layer;
forming a photoresist layer on the metal film layer;
exposing and developing the photoresist layer, to form a photoresist layer pattern, wherein the photoresist layer pattern comprises at least a first pattern region corresponding to a region where the diffuse reflection layer is arranged;
removing the metal film layer not covered by the photoresist layer pattern, to form a metal film layer pattern having an uneven surface, wherein the metal film layer pattern comprises a pattern of the diffuse reflection layer; and
stripping off the remaining photoresist layer.

14. The method of claim 13 , wherein the plasma process is a plasma descum process.

15. The method of claim 13 , wherein the photoresist layer pattern further comprises a second pattern region corresponding to a region wherein a light shielding layer for sheltering a thin film transistor of the array substrate from backlight is arranged, and the formed metal film layer pattern further comprises a pattern of the light shielding layer.

16. The method of claim 12 , wherein the plasma process is a plasma descum process.

17. The method of claim 12 , wherein the photoresist layer pattern further comprises a second pattern region corresponding to a region wherein a light shielding layer for sheltering a thin film transistor of the array substrate from backlight is arranged, and the formed metal film layer pattern further comprises a pattern of the light shielding layer.

18. The method of claim 12 , wherein an orthogonal projection of the diffuse reflection layer onto the base substrate at least partially overlaps an orthogonal projection of a corresponding one of the plurality of pixel regions onto the base substrate.

19. The method of claim 12 , wherein a material of the metal diffuse reflection layer comprises at least one of Ag, Au, Mo, Al, and Cu.

20. An array substrate, comprising a base substrate, a buffer layer, an active layer, a gate insulating layer, a gate metal layer, an interlayer dielectric layer, a source/drain metal laye

Assignees

• Boe Technology Group Co Ltd
• Ordos Yuansheng Optoelectronics Co Ltd

Inventors

• Yao Lei
• Shi Dawei
• Wang Wentao
• Yang Lu
• Xu Haifeng
• Yan Lei
• Wang Jinfeng
• Si Xiaowen
• Yan Fang
• Xue Jinjin
• Hou Lin
• Li Yuanbo
• Guo Zhixuan
• Li Xiaofang

Classifications

• H10P50/667

  by liquid etching only · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P76/2041

  Photolithographic processes · CPC title

• G02F1/136209 Primary

  Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element · CPC title

• H10K59/8791

  Arrangements for improving contrast, e.g. preventing reflection of ambient light · CPC title