Dynamic calibration of current sense for switching converters

Patent metadata

Field	Value
Publication number	US-10794982-B2
Application number	US-201816198643-A
Country	US
Kind code	B2
Filing date	Nov 21, 2018
Priority date	Nov 21, 2018
Publication date	Oct 6, 2020
Grant date	Oct 6, 2020

Abstract

A method for dynamic calibration of current sense for switching converters includes biasing a reference transistor with a Zero Temperature Coefficient current source, and a respective gate of each of the reference transistor and a power transistor with a gate voltage. The reference transistor and the power transistor each comprise a matching temperature coefficient. A reference voltage sensed across the reference transistor is multiplied by a gain, thereby generating a first calibration voltage, wherein the gain is determined by a gain coefficient. A transistor voltage sensed across the power transistor is multiplied by the gain, thereby generating a second calibration voltage. The first calibration voltage is compared to a target voltage to generate an error voltage. The gain coefficient is determined with an Analog to Digital Converter in response to the error voltage, thereby minimizing a difference between the target voltage and each of the calibration voltages.

First claim

What is claimed is:

1. A system for dynamic calibration of current sense for switching converters comprising:
a first one, a second one and a third one of a plurality of current sense channels configured to multiply a respective transistor voltage sensed across a respective transistor by a gain to generate a respective calibration voltage across a respective resistor, wherein the gain is determined by a gain coefficient, and each respective transistor has a matching temperature coefficient and a respective gate,
the respective transistor of the first one of the current sense channels connected between a voltage supply and a phase node, the respective calibration resistor connected to an output by a respective switch during a first phase, and the respective gate biased to a first voltage during the first phase,
the respective transistor of the second one of the current sense channels connected between the phase node and a ground, the respective calibration resistor connected to the output by a respective switch during a second phase not overlapping in time with the first phase, and the respective gate biased to the first voltage during the second phase,
the respective transistor of the third one of the current sense channels connected between a Zero Temperature Coefficient (ZTC) current source and the ground, and the respective gate biased to the first voltage;
a comparator configured to compare the respective calibration voltage of the third sense channel to a target voltage to generate an error voltage; and
an Analog to Digital Converter configured to convert the error voltage into the gain coefficient, thereby minimizing the error voltage and a difference between the target voltage and each respective calibration voltage.

2. The system of claim 1 wherein each of the current sense channels comprises a transconductance amplifier configured to sense the respective transistor voltage, a Multiplying Digital to Analog Converter configured to multiply an amplifier output current of the transconductance amplifier by the gain to provide a calibration current, and the calibration resistor configured to sink the calibration current to generate the calibration voltage.

3. The system of claim 1 wherein a latch is configured to store an averaged gain coefficient of a plurality of samples of the gain coefficient, and the gain of the first one and the second one of the current sense channels is determined by the averaged gain coefficient.

4. The system of claim 1 further comprising a load inductor connected between the phase node and a load capacitor, wherein a regulated voltage of the switching converter is formed on the load capacitor.

5. The system of claim 4 wherein the target voltage is determined by measuring a respective calibration voltage of the third one of the current sense channels corresponding the respective transistor biased to the first voltage and an average target current flowing though the load inductor.

6. The system of claim 1 wherein the gain coefficient is determined while the ZTC current source is activated with a pulsed source.

7. A method for dynamic calibration of current sense for switching converters comprising:
biasing a reference transistor with a Zero Temperature Coefficient (ZTC) current source, and a respective gate of each of the reference transistor and a power transistor with a gate voltage, wherein each of the reference transistor and the power transistor comprises a matching temperature coefficient;
multiplying a reference voltage sensed across the reference transistor by a first gain, thereby generating a first calibration voltage, wherein the first gain is determined by a gain coefficient;
multiplying a transistor voltage sensed across the power transistor by the first gain, thereby generating a second calibration voltage;
comparing the first calibration voltage to a target voltage to generate an error voltage; and
determining the gain coefficient with an Analog to Digital Converter in response to the error voltage, thereby minimizing the error voltage and a difference between the target voltage and each of the first calibration voltage and the second calibration voltage.

8. The method of claim 7 further comprising activating the ZTC current source with a pulsed current source, wherein the gain coefficient is determined while the ZTC current source is activated.

9. The method of claim 7 wherein generating the first calibration voltage further comprises sensing the reference voltage with a transconductance amplifier, converting an amplifier output of the transconductance amplifier with a Multiplying Digital to Analog Converter (MDAC) controlled by the first gain and generating the first calibration voltage by sinking an calibration current generated by the MDAC through a calibration resistor.

10. The method of claim 9 further comprising compensating for a difference in a transistor gain between the reference transistor and the power transistor by changing a second gain of the MDAC.

11. The method of claim 9 further comprising compensating for a difference in a transistor gain between the reference transistor and the power transistor by changing a first resistance value of the calibration resistor used to determine the first calibration voltage relative to a second resistance value of a second calibration resistor used to determine the second calibration voltage.

12. The method of claim 9 further comprising deactivating the transconductance amplifier in response to deactivating the power transistor.

13. The method of claim 7 further comprising determining the target voltage by measuring the first calibration voltage corresponding to the reference transistor biased by the gate voltage and an average target current flowing through a load inductor connected between a load capacitor and the power transistor.

14. An apparatus for dynamic calibration of current sense for switching converters comprising:
a first one of a plurality of current sense channels configured to multiply by a first gain, a first voltage sensed between a first drain and a first source of a first transistor, and to generate a first calibration voltage therefrom, wherein the first gain is defined by a gain coefficient, and wherein a first gate voltage on a first gate of the first transistor controls a first current flowing between the first drain and the first source;
a second one of the plurality of current sense channels configured to multiply by the first gain, a second voltage sensed between a second drain and a second source of a second transistor, and to generate a second calibration voltage therefrom, the second drain connected to a Zero Temperature Coefficient (ZTC) current source, the second source connected to a ground, a second gate of the second transistor biased to the first gate voltage and a first temperature coefficient of the first transistor equal to a second temperature coefficient of the second transistor;
a comparator configured to generate an error voltage from a difference between the second calibration voltage and a target voltage; and
an Analog to Digital Converter configured to determine the gain coefficient proportional to the error voltage, thereby minimizing the error voltage and a difference between the target voltage and each of the first calibration voltage and the second calibration voltage.

15. The apparatus of claim 14 wherein each of the current sense channels comprises a respective transconductance amplifier configured to sense a respective voltage between a respective drain and a respective source of the respective transistor, a respective Multiplying Digital to Analog Converte

Assignees

• Nxp Usa Inc

Inventors

• Newlin Trevor Mark

Classifications

• H02M1/0009

  Devices or circuits for detecting current in a converter · CPC title

• H02M1/0012

  Control circuits using digital or numerical techniques (in DC/DC converters H02M3/157, H02M3/33515; in DC-AC converters H02M7/53873) · CPC title

• G01R19/2513

  Arrangements for monitoring electric power systems, e.g. power lines or loads; Logging · CPC title

• G01R19/32

  Compensating for temperature change · CPC title

• G01R35/02 Primary

  of auxiliary devices, e.g. of instrument transformers according to prescribed transformation ratio, phase angle, or wattage rating · CPC title