Signal detection circuit and signal detection method

Patent metadata

Field	Value
Publication number	US-10794770-B2
Application number	US-201916277215-A
Country	US
Kind code	B2
Filing date	Feb 15, 2019
Priority date	Feb 19, 2018
Publication date	Oct 6, 2020
Grant date	Oct 6, 2020

Abstract

A signal detection circuit includes: a power terminal; a first current limitation circuit; a second current limitation circuit; a current-voltage conversion circuit; a first p-channel MOS transistor including a source, a gat, and a drain; a first n-channel MOS transistor including a drain, a gate, and a source; and a second n-channel MOS transistor in which a drain is connected to a first connection point connecting the resistor with the drain of the first n-channel MOS transistor, a gate is connected to a second connection point connecting the drain of the first p-channel MOS transistor with the current-voltage conversion circuit, and a source is grounded.

First claim

What is claimed is:

1. A signal detection circuit comprising:
a power terminal;
a first current limitation circuit connected to the power terminal;
a second current limitation circuit;
a resistor connected to the power terminal;
a current-voltage conversion circuit;
a first p-channel MOS transistor including a source connected to the power terminal via the first current limitation circuit, a gate to which a voltage changing in accordance with a change in a voltage level of an input voltage is supplied, and a drain grounded via the current-voltage conversion circuit;
a first n-channel MOS transistor including a drain connected to the power terminal via the resistor, a gate to which the voltage changing in accordance with the change in the voltage level of the input voltage is supplied, and a source grounded via the second current limitation circuit; and
a second n-channel MOS transistor in which a drain is connected to a first connection point connecting the resistor with the drain of the first n-channel MOS transistor, a gate is connected to a second connection point connecting the drain of the first p-channel MOS transistor with the current-voltage conversion circuit, and a source is grounded.

2. The signal detection circuit according to claim 1 ,
wherein the first current limitation circuit includes a first constant current source circuit and a first capacitor connected in parallel, and
wherein the second current limitation circuit includes a second constant current source circuit and a second capacitor connected in parallel.

3. The signal detection circuit according to claim 2 ,
wherein the current-voltage conversion circuit includes a third n-channel MOS transistor in which each of a gate and a drain are connected to the drain of the first p-channel MOS transistor and the gate of the second n-channel MOS transistor, and a source is grounded.

4. The signal detection circuit according to claim 3 , further comprising:
a third current limitation circuit; and
a second p-channel MOS transistor in which a source is connected to the power terminal, a gate is connected to the first connection point, and a drain is grounded via the third current limitation circuit.

5. The signal detection circuit according to claim 2 , further comprising:
a third current limitation circuit; and
a second p-channel MOS transistor in which a source is connected to the power terminal, a gate is connected to the first connection point, and a drain is grounded via the third current limitation circuit.

6. The signal detection circuit according to claim 1 ,
wherein the current-voltage conversion circuit includes a third n-channel MOS transistor in which each of a gate and a drain are connected to the drain of the first p-channel MOS transistor and the gate of the second n-channel MOS transistor, and a source is grounded.

7. The signal detection circuit according to claim 3 , further comprising:
a third current limitation circuit; and
a second p-channel MOS transistor in which a source is connected to the power terminal, a gate is connected to the first connection point, and a drain is grounded via the third current limitation circuit.

8. The signal detection circuit according to claim 1 , further comprising:
a third current limitation circuit; and
a second p-channel MOS transistor in which a source is connected to the power terminal, a gate is connected to the first connection point, and a drain is grounded via the third current limitation circuit.

9. A signal detection method, using a signal detection circuit including a power terminal, an input terminal, a first current limitation circuit connected to the power terminal, a second current limitation circuit, a resistor connected to the power terminal, a current-voltage conversion circuit, a first p-channel MOS transistor including a source connected to the power terminal via the first current limitation circuit, a gate to which a voltage changing in accordance with a change in a voltage level of an input voltage is supplied, and a drain grounded via a current-voltage conversion circuit, a first n-channel MOS transistor including a drain connected to the power terminal via the resistor, a gate to which a voltage changing in accordance with the change in the voltage level of the input voltage is supplied, and a source grounded via the second current limitation circuit, and a second n-channel MOS transistor in which a drain is connected to a first connection point connecting the resistor with the drain of the first n-channel MOS transistor, a gate is connected to a second connection point connecting the drain of the first p-channel MOS transistor with the current-voltage conversion circuit, and a source is grounded, comprising of:
amplifying a change in a signal voltage supplied from the input terminal to a positive voltage side by the resistor and the first n-channel MOS transistor; and
amplifying a change in a signal voltage supplied from the input terminal to a negative voltage side by the resistor and the second n-channel MOS transistor.

10. The signal detection method according to claim 9 ,
wherein the first current limitation circuit includes a first current limitation circuit and a first capacitor connected in parallel, and
wherein the second current limitation circuit includes a second current limitation circuit and a second capacitor connected in parallel.

Assignees

• Ablic Inc
• Ritsumeikan Trust

Inventors

• Utsunomiya Fumiyasu
• Douseki Takakuni
• Tanaka Ami

Classifications

• G01J5/35 Primary

  Electrical features thereof · CPC title

• G01J2001/444

  Compensating; Calibrating, e.g. dark current, temperature drift, noise reduction or baseline correction; Adjusting · CPC title

• G01J1/44 Primary

  Electric circuits {(for command of an exposure part G03B7/02)} · CPC title

• G01J2001/4406

  Plural ranges in circuit, e.g. switchable ranges; Adjusting sensitivity selecting gain values · CPC title

• G01R19/00

  Arrangements for measuring currents or voltages or for indicating presence or sign thereof (G01R5/00 takes precedence; for measuring bioelectric currents or voltages A61B5/24) · CPC title