Hybrid high electron mobility transistor and active matrix structure

Patent metadata

Field	Value
Publication number	US-10790336-B2
Application number	US-201916377169-A
Country	US
Kind code	B2
Filing date	Apr 6, 2019
Priority date	Apr 27, 2015
Publication date	Sep 29, 2020
Grant date	Sep 29, 2020

Abstract

Hybrid high electron mobility field-effect transistors including inorganic channels and organic gate barrier layers are used in some applications for forming high resolution active matrix displays. Arrays of such high electron mobility field-effect transistors are electrically connected to thin film switching transistors and provide high drive currents for passive devices such as organic light emitting diodes. The organic gate barrier layers are operative to suppress both electron and hole transport between the inorganic channel layer and the gate electrodes of the high electron mobility field-effect transistors.

First claim

What is claimed is:

1. An active matrix structure comprising:
a backplane including an array of high electron mobility field-effect driver transistors, each of the high electron mobility field-effect driver transistors including:
an inorganic, crystalline semiconductor layer;
a gate electrode;
first and second ohmic contacts operatively associated with the inorganic semiconductor layer, and
a gate barrier layer operatively associated with the gate electrode, the gate barrier layer being positioned between the gate electrode and a channel region of the inorganic semiconductor layer and including one or more organic semiconductor layers operative to suppress electron and hole transport between the inorganic semiconductor layer and the gate electrode;
the backplane further including an array of thin film switching transistors, each of the thin film switching transistors being electrically connected to one of the high electron mobility field-effect driver transistors, and

a frontplane including an array of passive electronic devices, each of the passive electronic devices being electrically connected to one of the high electron mobility field-effect driver transistors.

2. The active matrix structure of claim 1 , wherein the inorganic semiconductor layer comprises n-type crystalline silicon.

3. The active matrix structure of claim 1 , wherein the gate barrier layer of each high electron mobility field-effect driver transistor further includes a first organic semiconductor layer comprising a first material for blocking holes and a second organic semiconductor layer comprised of a second material for blocking electrons, the first material being different from the second material.

4. The active matrix structure of claim 3 , further including an electrically insulating layer, wherein each of the thin film switching transistors further includes an inorganic semiconductor channel layer adjoining a first side of the electrically insulating layer and the inorganic, crystalline semiconductor layer of each high electron mobility field-effect driver transistor adjoins a second side of the electrically insulating layer.

5. The active matrix structure of claim 4 , wherein the inorganic, crystalline semiconductor layer of each high electron mobility field-effect driver transistor includes monocrystalline silicon.

6. The active matrix structure of claim 5 , wherein the first organic semiconductor layer of each high electron mobility field-effect driver transistor adjoins the gate electrode thereof and the second organic semiconductor layer of each high electron mobility field-effect driver transistor is positioned between the first organic semiconductor layer and the channel region of the inorganic semiconductor layer thereof.

7. The active matrix structure of claim 1 , wherein the array of passive electronic devices includes organic light emitting diodes.

8. The active matrix structure of claim 1 , further including an organic passivation layer between the channel region of the inorganic semiconductor layer and the gate barrier layer.

9. The active matrix structure of claim 1 , wherein the inorganic, crystalline semiconductor layer comprises dopants.

10. The active matrix structure of claim 1 , wherein the channel region of the inorganic, crystalline semiconductor layer comprises p-type silicon and further wherein each of the high electron mobility field-effect driver transistors is configured as an inversion-type high electron mobility field-effect transistor.

11. The active matrix structure of claim 1 , wherein the channel region of the inorganic, crystalline semiconductor layer comprises n-type or undoped silicon and further wherein each of the high electron mobility field-effect driver transistors is configured as an accumulation-type high electron mobility field-effect transistor.

12. The active matrix structure of claim 1 , wherein the gate barrier layer of each high electron mobility field-effect driver transistor further includes a first organic semiconductor layer comprising a first material for blocking holes and a second organic semiconductor layer comprised of a second material for blocking electrons, the first material being different from the second material, and wherein the first organic semiconductor layer adjoins the gate electrode.

13. The active matrix structure of claim 12 , wherein each of the high electron mobility field-effect driver transistors is configured as an inversion-type high electron mobility field-effect transistor, and further wherein the channel region of the inorganic, crystalline semiconductor layer comprises p-type silicon.

14. The active matrix structure of claim 12 , wherein each of the high electron mobility field-effect driver transistors is configured as an accumulation-type high electron mobility field-effect transistor, and further wherein the channel region of the inorganic, crystalline semiconductor layer comprises n-type or undoped silicon.

15. An active matrix structure comprising:
a backplane including an array of high electron mobility field-effect driver transistors, each of the high electron mobility field-effect driver transistors including:
an inorganic, crystalline semiconductor layer;
a gate electrode;
first and second ohmic contacts operatively associated with the inorganic semiconductor layer;
a gate barrier layer operatively associated with the gate electrode, the gate barrier layer being positioned between the gate electrode and the inorganic semiconductor layer and including one or more organic semiconductor layers operative to suppress electron and hole transport between the inorganic semiconductor layer and the gate electrode; and
an organic passivation layer between the inorganic semiconductor layer and the gate barrier layer;
the backplane further including an array of thin film switching transistors, each of the thin film switching transistors being electrically connected to one of the high electron mobility field-effect driver transistors, and

a frontplane including an array of passive electronic devices including organic light emitting diodes, each of the passive electronic devices being electrically connected to one of the high electron mobility field-effect driver transistors.

16. The active matrix structure of claim 15 , wherein the gate barrier layer of each high electron mobility field-effect driver transistor further includes a first organic semiconductor layer comprising a first material for blocking holes and a second organic semiconductor layer comprised of a second material for blocking electrons, the first material being different from the second material.

17. The active matrix structure of claim 16 , wherein the first organic semiconductor layer of each high electron mobility field-effect driver transistor adjoins the gate electrode thereof and the second organic semiconductor layer of each high electron mobility field-effect driver transistor is positioned between the first organic semiconductor layer and the inorganic semiconductor layer thereof.

18. The active matrix structure of claim 17 , wherein the thin film switching transistors comprise organic thin film transistors.

19. The active matrix structure of claim 17 , wherein the inorganic, crystalline semiconductor layer includes first and second highly doped source/drain regions, the first and second ohmic contacts being positioned, respectively, on the first and second highly doped source/drain regions.

20. The active matrix structure of claim 17 , wherein the inorganic semiconductor layer com

Assignees

• IBM

Inventors

• Afzali-Ardakani Ali
• Hekmatshoartabari Bahman
• Sadana Devendra K
• Shahrjerdi Davood

Classifications

• H10D88/01

  Manufacture or treatment · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D64/602

  Heterojunction gate electrodes for FETs · CPC title

• H10D87/00

  Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate · CPC title

• H10D86/471

  having different architectures, e.g. having both top-gate and bottom-gate TFTs · CPC title