High voltage integration for HKMG technology

Patent metadata

Field	Value
Publication number	US-10790279-B2
Application number	US-201916656756-A
Country	US
Kind code	B2
Filing date	Oct 18, 2019
Priority date	Sep 13, 2017
Publication date	Sep 29, 2020
Grant date	Sep 29, 2020

Abstract

The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a low voltage transistor device is disposed in a low voltage region defined on a substrate. The low voltage transistor device comprises a low voltage gate electrode and a first gate dielectric separating the low voltage gate electrode from the substrate. A high voltage transistor device is disposed in a high voltage region defined on the substrate. The high voltage transistor device comprises a high voltage gate electrode and a high voltage gate dielectric separating the high voltage gate electrode from the substrate. A first interlayer dielectric layer is disposed over the substrate surrounding the low voltage transistor device and the high voltage transistor device. The high voltage gate electrode is disposed on the first interlayer dielectric layer and separated from the substrate by the first interlayer dielectric layer.

First claim

What is claimed is:

1. An integrated circuit (IC), comprising:
a low voltage region and a high voltage region integrated in a substrate;
a low voltage transistor device disposed in the low voltage region and configured to operate at a first operation voltage, the low voltage transistor device comprising a low voltage gate electrode and a low voltage gate dielectric separating the low voltage gate electrode from the substrate;
a high voltage transistor device disposed in the high voltage region and configured to operate at an operation voltage greater than the first operation voltage, the high voltage transistor device comprising a high voltage gate electrode and a high voltage gate dielectric separating the high voltage gate electrode from the substrate; and
a first interlayer dielectric layer disposed over the substrate surrounding the low voltage transistor device and the high voltage transistor device;
wherein the high voltage gate electrode is disposed on the first interlayer dielectric layer and separated from the substrate by the first interlayer dielectric layer.

2. The IC of claim 1 , wherein the high voltage gate electrode is disposed within a second interlayer dielectric layer that overlies the first interlayer dielectric layer, wherein the first interlayer dielectric layer is a gate dielectric component of the high voltage gate dielectric that separates the high voltage gate electrode from the substrate.

3. The IC of claim 2 , further comprising a first metal line disposed within the second interlayer dielectric layer and coupled to the low voltage gate electrode through a first contacting via.

4. The IC of claim 3 , wherein the first metal line has a bottom surface aligned with that of the high voltage gate electrode.

5. The IC of claim 1 , wherein the low voltage gate electrode is a metal gate electrode.

6. The IC of claim 1 , wherein the first interlayer dielectric layer extends across the low voltage region over the low voltage gate electrode.

7. The IC of claim 1 , wherein the high voltage gate dielectric comprises an oxide component disposed between the first interlayer dielectric layer and the substrate.

8. The IC of claim 7 , wherein the oxide component contacts an upper surface of the substrate.

9. The IC of claim 8 , further comprising a sidewall spacer disposed along sidewalls of the low voltage gate dielectric and the oxide component of the high voltage gate dielectric.

10. The IC of claim 9 , further comprising a hard mask disposed on the low voltage gate electrode and contacting top surfaces of the sidewall spacer.

11. The IC of claim 7 , wherein the high voltage gate dielectric further comprises a high-k dielectric component disposed between the oxide component and the first interlayer dielectric layer.

12. The IC of claim 1 , wherein the high voltage gate dielectric further comprises a high-k dielectric component disposed between an oxide component and the substrate.

13. The IC of claim 1 , wherein the first interlayer dielectric layer is a low-k dielectric material.

14. A method of forming an integrated circuit (IC), comprising:
providing a substrate having a low voltage region and a high voltage region defined on the substrate;
forming and patterning a high voltage gate dielectric component on the substrate within the high voltage region and a low voltage gate dielectric component on the substrate within the low voltage region;
forming a low voltage gate electrode on the low voltage gate dielectric component;
forming a first interlayer dielectric layer overlying the low voltage gate electrode in the low voltage region and the high voltage gate dielectric component in the high voltage region; and
forming a high voltage gate electrode overlying the first interlayer dielectric layer in the high voltage region.

15. The method of claim 14 , further comprising forming a high-k dielectric layer on the high voltage gate dielectric component within the high voltage region prior to forming the first interlayer dielectric layer.

16. The method of claim 14 , wherein forming the low voltage gate electrode comprises:
forming and patterning a first polysilicon layer over the low voltage gate dielectric component in the low voltage region; and
forming and patterning a second polysilicon layer directly on the first polysilicon layer in the low voltage region and on the high voltage gate dielectric component in the high voltage region.

17. The method of claim 16 , further comprising replacing the second polysilicon layer and the first polysilicon layer in the low voltage region by a metal material.

18. The method of claim 16 , further comprising:
removing the second polysilicon layer from the high voltage region prior to forming the first interlayer dielectric layer.

19. A method of forming an integrated circuit (IC), comprising:
providing a substrate having a low voltage region, a medium voltage region, and a high voltage region defined on the substrate;
forming and patterning a high voltage gate dielectric component on the substrate in the high voltage region, a medium voltage gate dielectric component on the substrate in the medium voltage region, and a low voltage gate dielectric component on the substrate in the low voltage region;
forming a first polysilicon layer on the high voltage gate dielectric component in the high voltage region, on the medium voltage gate dielectric component in the medium voltage region, and on the low voltage gate dielectric component in the low voltage region;
forming a second polysilicon layer on the first polysilicon layer within the low voltage region;
patterning the second polysilicon layer and the first polysilicon layer to form a low voltage gate electrode in the low voltage region, to form a medium voltage gate electrode in the medium voltage region, and to expose the high voltage gate dielectric component on the substrate in the high voltage region; and
forming a first interlayer dielectric layer overlying the low voltage gate electrode, the medium voltage gate electrode, and the high voltage gate dielectric component.

20. The method of claim 19 , further comprising:
forming a second interlayer dielectric layer over the first interlayer dielectric layer; and
forming contact vias through the first interlayer dielectric layer and respectively reaching on the low voltage gate electrode and the medium voltage gate electrode;
forming a first metal layer in the second interlayer dielectric layer;
wherein the first metal layer is formed including metal lines in the low voltage region and the high voltage region electrically coupled to the contact vias and a high voltage gate electrode overlying the high voltage gate dielectric component in the high voltage region.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Thei Kong-Beng
• Chou Chien-Chih
• Fan Fu-Jier
• Tuan Hsiao-Chin
• Chen yi-huan
• Kalnitsky Alexander
• Chen Yi-Sheng

Classifications

• H10D84/856

  the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS · CPC title

• H10D89/00

  Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00 · CPC title

• H10D84/0181

  Manufacturing their gate insulating layers · CPC title

• H10D84/0172

  Manufacturing their gate conductors · CPC title

• H10D84/0144

  Manufacturing their gate insulating layers · CPC title