Integrated circuit die having backside passive components and methods associated therewith

Patent metadata

Field	Value
Publication number	US-10790263-B2
Application number	US-201916287915-A
Country	US
Kind code	B2
Filing date	Feb 27, 2019
Priority date	Sep 26, 2014
Publication date	Sep 29, 2020
Grant date	Sep 29, 2020

Abstract

Embodiments of the present disclosure are directed towards an integrated circuit (IC) die. In embodiments, the IC die may include a semiconductor substrate, a plurality of active components disposed on a first side of the semiconductor substrate, and a plurality of passive components disposed on a second side of the semiconductor substrate. In embodiments the second side may be disposed opposite the first side. The passive components may, in some embodiments, include capacitors and/or resistors while the active components may, in some embodiments, include transistors. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. An integrated circuit (IC) package assembly comprising:
an integrated circuit (IC) die having:
a plurality of active components disposed on a first side of a semiconductor substrate;
a plurality of passive components disposed on a second side of the semiconductor substrate, wherein the second side of the semiconductor substrate is disposed opposite the first side of the semiconductor substrate, wherein the plurality of passive components comprise two or more trench capacitors, wherein each of the two or more trench capacitors include a first metal layer disposed on one or more trenches formed in the semiconductor substrate, a capacitor dielectric layer disposed on the first metal layer, and a second metal layer disposed on the capacitor dielectric layer, wherein the first metal layer is electrically coupled with a through-silicon via (TSV) in the semiconductor substrate, wherein the TSV electrically couples the first side of the semiconductor substrate with the second side of the semiconductor substrate;
a first plurality of input/output (I/O) interconnect structures electrically coupled with the plurality of active components; and
a second plurality of I/O interconnect structures electrically coupled with the plurality of passive components, wherein the second plurality of I/O interconnect structures includes an electrical routing structure electrically coupled to the second metal layer of at least one of the trench capacitors, wherein the electrical routing structure is selected from the group consisting of:
an additional TSV disposed in the semiconductor substrate, wherein the additional TSV electrically couples the first side of the substrate with the second side of the semiconductor substrate; or
an interconnect structure disposed in one or more redistribution layers (RDLs) that are disposed on the second side of the semiconductor substrate; and

a package substrate electrically coupled with the IC die, wherein the package substrate is configured to route electrical signals of the IC die.

2. The IC package assembly of claim 1 , wherein the IC die is a first IC die and further comprising a second IC die disposed on the second side of the semiconductor substrate, wherein the second IC die includes a third plurality of I/O interconnect structures coupled with the second plurality of I/O interconnect structures to route electrical signals between the first IC die and the second IC die.

3. The IC package assembly of claim 1 , wherein the passive components further include one or more of:
metal-insulator-metal (MIM) capacitors; or
thin film resistors.

4. The IC package assembly of claim 1 , wherein the IC die further comprises one or more layers of electrically insulative material disposed on the first side of the semiconductor substrate, wherein the one or more layers of electrically insulative material encapsulate the plurality of active components;
a plurality of die-level interconnects disposed in the one or more layers of the electrically insulative material; and
electrical routing features disposed in the one or more layers of electrically insulative material, wherein the electrical routing features are configured to electrically couple the die-level interconnects with the plurality of active components.

5. The IC package assembly of claim 4 , wherein the one or more layers of electrically insulative material are one or more first layers of electrically insulative material, the electrical routing features are first electrical routing features, and the IC die further comprising:
one or more redistribution layers (RDLs) disposed on the second side of the semiconductor substrate, wherein the one or more redistribution layers include:
one or more second layers of electrically insulative material disposed on the second side of the semiconductor substrate, wherein the one or more second layers of electrically insulative material encapsulate the plurality of passive components;
a plurality of input/output (I/O) interconnect structures disposed in the one or more second layers of the electrically insulative material; and
second electrical routing features disposed in the one or more second layers of electrically insulative material, wherein the second electrical routing features are configured to electrically couple the plurality of I/O interconnect structures with the plurality of passive components.

6. The IC package assembly of claim 1 , wherein the plurality of passive components further comprise a plurality of metal-insulator-metal (MIM) capacitors, wherein each of the plurality of MIM capacitors include a first metal layer, a capacitor dielectric layer disposed on the first metal layer, and a second metal layer disposed on the capacitor dielectric layer.

7. The IC package assembly of claim 6 , wherein the first and second metal layers of each of the plurality of MIMs are respectively electrically coupled with first and second interconnect structures disposed in one or more redistribution layers (RDLs) that are disposed on the second side of the semiconductor substrate.

8. The IC package assembly of claim 1 , wherein the plurality of passive components further comprise a plurality of thin film resistors wherein each thin film resistor includes a first terminal and a second terminal.

9. The IC package assembly of claim 8 , wherein the first and second terminals are respectively electrically coupled with first and second interconnect structures disposed in one or more redistribution layers (RDLs) that are disposed on the second side of the semiconductor substrate.

10. The IC package assembly of claim 1 , wherein the electrical routing structure is the additional TSV.

11. The IC package assembly of claim 1 , wherein the electrical routing structure is the interconnect structure.

Assignees

• Intel Corp

Inventors

• Lee Kevin J

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W70/695

  Organic materials · CPC title

• H10W20/49

  Adaptable interconnections, e.g. fuses or antifuses · CPC title

• H10W20/498

  Resistive arrangements or effects of, or between, wiring layers · CPC title