Discrete electronic component comprising a transistor

Patent metadata

Field	Value
Publication number	US-10790249-B2
Application number	US-201916449408-A
Country	US
Kind code	B2
Filing date	Jun 23, 2019
Priority date	Jun 25, 2018
Publication date	Sep 29, 2020
Grant date	Sep 29, 2020

Abstract

The invention concerns a discrete electronic component including: a semiconductor chip including a transistor, the chip including a first metallization of connection to a first conduction region of the transistor; and a printed circuit board including first and second separate connection pads, wherein: the chip is assembled on the printed circuit board so that the first metallization of the chip is in contact with the first and second connection pads of the printed circuit board; and the assembly including the semiconductor chip and the printed circuit board is encapsulated in a package made of an insulating material leaving access to first and second connection terminals of the component connected, inside of the package, respectively to the first and second connection pads of the printed circuit board.

First claim

What is claimed is:

1. A discrete electronic component comprising:
a semiconductor chip comprising a transistor, the chip comprising a first metallization of connection to a first conduction region of the transistor, a second metallization of connection to a second conduction region of the transistor, and a third metallization of connection to a control region of the transistor; and
a printed circuit board comprising first, second, third, and fourth separate connection pads,
wherein:
the chip is assembled on the printed circuit board so that the first metallization of the chip is in contact with the first and second connection pads of the printed circuit board, and so that the second and third metallizations of the chip are respectively in contact with the third, and fourth connection pads of the printed circuit board; and
an assembly comprising the semiconductor chip and the printed circuit board is encapsulated in a package made of an insulating material leaving access to first, second, third, and fourth connection terminals of the component, connected, inside of the package, respectively to the first, second, third, and fourth connection pads of the printed circuit board.

2. The component of claim 1 , wherein in top view, a distance between the second pad of the printed circuit board and the fourth pad of the printed circuit board is shorter than one tenth of a largest dimension of the chip.

3. The component of claim 1 , wherein the connection pads of the printed circuit board are made of metal.

4. The component of claim 3 , wherein the connection pads of the printed circuit board are made of copper.

5. The component of claim 1 , wherein the transistor is a MOS transistor, the first conduction region being a source region of the transistor.

6. The component of claim 5 , wherein the second conduction region is a drain region of the transistor and the control region is a gate region of the transistor.

7. The component of claim 1 , wherein the transistor is a gallium nitride transistor, a silicon carbide MOS transistor, or a silicon superjunction MOS transistor.

8. The component of claim 1 , wherein the connection terminals of the component are metal pins.

9. The component of claim 1 , wherein the connection terminals of the component are metal pads.

Assignees

• Commissariat Energie Atomique

Inventors

• Carcouet Sébastien
• Maynard Xavier

Classifications

• H10W90/794

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/755

  between a chip and a laterally-adjacent insulating package substrate, interpose or RDL · CPC title

• H10W72/59

  Bond pads specially adapted therefor · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title

• H10W72/50

  Bond wires · CPC title