Inductor structure for integrated circuit

Patent metadata

Field	Value
Publication number	US-10790194-B2
Application number	US-201916584809-A
Country	US
Kind code	B2
Filing date	Sep 26, 2019
Priority date	Oct 25, 2017
Publication date	Sep 29, 2020
Grant date	Sep 29, 2020

Abstract

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first plurality of conductive interconnect layers arranged within a first inter-level dielectric (ILD) structure disposed on a first surface of a first substrate. A second plurality of conductive interconnect layers are arranged within a second ILD structure disposed on a first surface of a second substrate. The second substrate is separated from the first substrate by the first ILD structure. The first plurality of conductive interconnect layers and the second plurality of conductive interconnect layers define an inductor having one or more turns.

First claim

What is claimed is:

1. An integrated chip, comprising:
a first plurality of conductive interconnect layers arranged within a first inter-level dielectric (ILD) structure disposed on a first surface of a first substrate;
a second plurality of conductive interconnect layers arranged within a second ILD structure disposed on a first surface of a second substrate, the second substrate separated from the first substrate by the first ILD structure;
wherein the first plurality of conductive interconnect layers and the second plurality of conductive interconnect layers define an inductor having one or more turns;
wherein the first plurality of conductive interconnect layers defining the inductor comprise a first via having a top surface that is narrower than a bottom surface; and
wherein the second plurality of conductive interconnect layers defining the inductor comprise a second via having a top surface that is wider than a bottom surface.

2. The integrated chip of claim 1 , wherein the inductor wraps around an axis that is oriented in parallel to the first surface of the first substrate.

3. The integrated chip of claim 1 , wherein the second substrate is separated from the first substrate by the second ILD structure.

4. The integrated chip of claim 1 , further comprising:
a passivation layer disposed along a second surface of the first substrate opposing the first surface;
one or more redistribution layers separated from the first substrate by the passivation layer; and
one or more through-substrate-vias (TSVs) extending through the first substrate and electrically coupled to the one or more redistribution layers, wherein the inductor is further defined by the one or more redistribution layers and the one or more TSVs.

5. The integrated chip of claim 4 , wherein the one or more TSVs respectively have a width that increases as a distance from the one or more redistribution layers decreases.

6. The integrated chip of claim 1 , wherein the first plurality of conductive interconnect layers comprise a first conductive interconnect layer having a larger height than one or more of the second plurality of conductive interconnect layers.

7. An integrated chip, comprising:
a first plurality of conductive interconnect layers disposed within a first inter-level dielectric (ILD) structure on a first surface of a first substrate;
one or more redistribution layers disposed within one or more dielectric structures on a second surface of the first substrate that opposes the first surface;
a bond pad coupled to the one or more redistribution layers, wherein the one or more redistribution layers are vertically between the bond pad and the first substrate;
a plurality of through-substrate-vias (TSVs) extending through the first substrate and coupling the first plurality of conductive interconnect layers to the one or more redistribution layers; and
wherein the one or more redistribution layers define at least a part of an inductor having one or more turns that wind around an axis.

8. The integrated chip of claim 7 , wherein the axis extends in parallel to the first surface of the first substrate.

9. The integrated chip of claim 7 , wherein the inductor is completely confined within the one or more dielectric structures.

10. The integrated chip of claim 7 , wherein an entirety of the inductor is laterally separated from the plurality of TSVs by a non-zero distance.

11. The integrated chip of claim 7 ,
wherein a first one of the one or more redistribution layers defines a top of the inductor; and
wherein a second one of the one or more redistribution layers contacts the bond pad at a position that is laterally outside of the first one of the one or more redistribution layers.

12. The integrated chip of claim 7 , wherein a first one of the one or more redistribution layers defines a top of the inductor and contacts a bottom of the bond pad.

13. The integrated chip of claim 7 , wherein the one or more redistribution layers comprise:
a first redistribution wire; and
a second redistribution wire vertically separated from the first redistribution wire by a redistribution via, wherein the second redistribution wire defines a top of the inductor and laterally extends past an outermost sidewall of the first redistribution wire.

14. The integrated chip of claim 7 ,
wherein the one or more dielectric structures comprise a first dielectric layer and a second dielectric layer over the first dielectric layer; and
wherein the one or more redistribution layers comprise a redistribution via laterally surrounded by the first dielectric layer and a redistribution wire laterally surrounded by the second dielectric layer, the redistribution via directly contacting a first one of the plurality of TSVs.

15. The integrated chip of claim 7 , wherein all of the plurality of TSVs that define the inductor are arranged along outermost edges of the inductor.

16. An integrated chip, comprising:
a first plurality of conductive routing layers disposed within a first dielectric structure along a first surface of a first substrate;
a second plurality of conductive routing layers disposed within a second dielectric structure along a second surface of the first substrate opposing the first surface;
a passivation layer disposed on the second surface of the first substrate and separating the second plurality of conductive routing layers from the first substrate;
a plurality of through-substrate-vias (TSVs) extending through the first substrate and coupling the first plurality of conductive routing layers to the second plurality of conductive routing layers; and
wherein the first plurality of conductive routing layers, the second plurality of conductive routing layers, or the plurality of TSVs define an inductor having one or more turns that wind around an axis extending in parallel to the first surface of the first substrate.

17. The integrated chip of claim 16 , wherein an entirety of the inductor is arranged above or below the plurality of TSVs.

18. The integrated chip of claim 16 , wherein a bottommost one of the second plurality of conductive routing layers that is over the passivation layer defines a top of the inductor.

19. The integrated chip of claim 16 ,
wherein the first plurality of conductive routing layers comprise a first via having a top surface that is narrower than a bottom surface; and
wherein the second plurality of conductive routing layers comprise a second via having a top surface that is wider than a bottom surface.

20. The integrated chip of claim 16 ,
wherein the first plurality of conductive routing layers comprise an interconnect wire defining a bottom of the inductor; and
wherein the plurality of TSVs that define the inductor directly contact the interconnect wire.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Shih-Han
• Wang Ching-Chun
• Yaung Dun-Nian
• Lin Hsing-Chih
• Liu Jen-Cheng
• Kao Min-Feng

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/934

  Cross-sectional shape, i.e. in side view · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title