Semiconductor device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-10790150-B2
Application number	US-201916682725-A
Country	US
Kind code	B2
Filing date	Nov 13, 2019
Priority date	Jun 1, 2017
Publication date	Sep 29, 2020
Grant date	Sep 29, 2020

Abstract

A method for fabricating a semiconductor device includes: preparing a substrate; forming an isolation layer defining an active region in the substrate; forming a first insulation structure over the substrate, the first insulation structure defining a line-type opening that exposes the isolation layer and the active region; forming a plug pad through a Selective Epitaxial Growth (SEG) process over the exposed active regions; forming a second insulation structure inside the line-type opening, the second insulation structure defining a contact hole landing on the plug pad; and filling the contact hole with a contact plug.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate including an active region and an isolation layer;
a plurality of bit lines over the semiconductor substrate;
a line-type opening that is formed between the bit lines and includes a recess which exposes the active region and the isolation layer;
a plug pad that is formed inside the recess and contacts the active region;
a plug isolation structure that is formed inside the line-type opening to expose the plug pad and defines a contact hole having a smaller landing area than a surface area of an upper portion of the plug pad; and
a contact plug formed inside the contact hole,
wherein the plug pad comprising:
a central portion formed on the active region; and
a side extended portion that laterally grows up from the central portion to extend over the isolation layer.

2. The semiconductor device of claim 1 , wherein the plug pad includes an epitaxial layer.

3. The semiconductor device of claim 1 , wherein the plug pad includes a SEG-Si or SEG-SiP.

4. The semiconductor device of claim 1 , wherein the plug isolation structure includes:
a spacer that is formed on both side walls of the line-type opening; and
a plug isolation layer that is formed inside the line-type opening where the spacer is formed, and
the contact hole is defined by being self-aligned to the plug isolation layer and the spacer.

5. The semiconductor device of claim 1 , further comprising:
a word line buried in the semiconductor substrate;
first and second source/drain regions that are formed in the semiconductor substrate on both sides of the word line;
a bit line contact plug formed on the first source/drain region; and
a bit line formed on the bit line contact plug,
wherein the plug pad is coupled to the second source/drain region.

6. The semiconductor device of claim 1 , further comprising:
a memory element formed over the contact plug.

Assignees

• Sk Hynix Inc

Inventors

• Kim Oh-Hyun
• Ahn Sung-Hwan
• Park Hae-Jung
• Ahn Tae-Hang

Classifications

• H10D64/0113 Primary

  the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/075

  of multilayered thin functional dielectric layers · CPC title

• H10W20/069 Primary

  by forming self-aligned vias or self-aligned contact plugs · CPC title