Image processor with configurable number of active cores and supporting internal network

Patent metadata

Field	Value
Publication number	US-10789202-B2
Application number	US-201715594502-A
Country	US
Kind code	B2
Filing date	May 12, 2017
Priority date	May 12, 2017
Publication date	Sep 29, 2020
Grant date	Sep 29, 2020

Abstract

A method is described. The method includes configuring a first instance of object code to execute on a processor. The processor has multiple cores and an internal network. The internal network is configured in a first configuration that enables a first number of the cores to be communicatively coupled. The method also includes configuring a second instance of the object code to execute on a second instance of the processor. A respective internal network of the second instance of the processor is configured in a second configuration that enables a different number of cores to be communicatively coupled, wherein, same positioned cores on the processor and the second instance of the processor have same network addresses for the first and second configurations. A processor is also described having an internal network designed to enable the above method.

First claim

The invention claimed is:

1. A non transitory machine readable storage medium comprising program code that when processed by a computing system causes a method to be performed, the method comprising:
configuring a first instance of object code to execute on a first configuration of a processor, the processor having multiple cores and an internal network, the internal network of the first configuration of the processor configured in a first configuration that enables a first number of the multiple cores to be communicatively coupled; and,
configuring a second instance of the object code to execute on a second configuration of the processor, a respective internal network of the second configuration of the processor configured in a second configuration that enables a second number of multiple cores to be communicatively coupled, wherein, same positioned cores of the first configuration of the processor and the second configuration of the processor have same network addresses,
wherein the first instance of the object code and the second instance of the object code (i) execute on different sets of cores of the processor, and (ii) address cores in the different sets of cores as offsets from a same base address.

2. The non-transitory machine readable medium of claim 1 wherein one of the first and second instances of the object code is to execute as a smaller component of code within a larger application on its respective configuration of the processor, wherein the larger application is constructed by combining an object code instance of another program with the one of the first and second instances of the object code.

3. The non-transitory machine readable medium of claim 2 wherein the other of the first and second instances of the object code is to execute as a stand alone application on its respective configuration of the processor.

4. The non-transitory machine readable medium of claim 1 wherein the method further comprises:
configuring a third instance of the object code to execute on another configuration of the processor that enables a different number of cores.

5. A computing system, comprising:
multiple cores;
a system memory;
a system memory controller between the system memory and the multiple cores;
a non transitory machine readable storage medium storing program code that, when processed by the multiple cores, cause the multiple cores to perform operations comprising:
configuring a first instance of object code to execute on a first configuration of a processor, the processor having the multiple cores and an internal network, the internal network of the first configuration of the processor configured in a first configuration that enables a first number of the multiple cores to be communicatively coupled; and,
configuring a second instance of the object code to execute on a second configuration of the processor, a respective internal network of the second configuration of the processor configured in a second configuration that enables a second number of multiple cores to be communicatively coupled, wherein, same positioned cores of the first configuration of the processor and the second configuration of the processor have same network addresses,
wherein the first instance of the object code and the second instance of the object code (i) execute on different sets of cores of the processor, and (ii) address cores in the different sets of cores as offsets from a same base address.

6. The computing system of claim 5 wherein one of the first and second instances of the object code is to execute as a smaller component of code within a larger application on its respective configuration of the processor, wherein the larger application is constructed by combining an object code instance of another program with the one of the first and second instances of the object code.

7. The computing system of claim 6 wherein the other of the first and second instances of the object code is to execute as a stand alone application on its respective configuration of the processor.

8. The computing system of claim 5 wherein the processor is an image processor.

9. A computer-implemented method comprising:
configuring a first instance of object code to execute on a first configuration of a processor, the processor having multiple cores and an internal network, the internal network of the first configuration of the processor configured in a first configuration that enables a first number of the multiple cores to be communicatively coupled; and,
configuring a second instance of the object code to execute on a second configuration of the processor, a respective internal network of the second configuration of the processor configured in a second configuration that enables a second number of multiple cores to be communicatively coupled, wherein, same positioned cores of the first configuration of the processor and the second configuration of the processor have same network addresses,
wherein the first instance of the object code and the second instance of the object code (i) execute on different sets of cores of the processor, and (ii) address cores in the different sets of cores as offsets from a same base address.

10. The method of claim 9 , wherein one of the first and second instances of the object code is to execute as a smaller component of code within a larger application on its respective configuration of the processor, wherein the larger application is constructed by combining an object code instance of another program with the one of the first and second instances of the object code.

11. The method of claim 10 , wherein the other of the first and second instances of the object code is to execute as a stand alone application on its respective configuration of the processor.

12. The method of claim 9 , wherein the method further comprises:
configuring a third instance of the object code to execute on another configuration of the processor that enables a different number of cores.

Assignees

• Google Llc

Inventors

• Redgrave Jason
• Meixner Albert
• Kim Ji
• Shacham Ofer

Classifications

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06F15/8023

  Two dimensional arrays, e.g. mesh, torus · CPC title

• G06F15/17375 Primary

  One dimensional, e.g. linear array, ring · CPC title

• G06F1/3243 Primary

  Power saving in microcontroller unit · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title