Maintaining multiple cache areas

Patent metadata

Field	Value
Publication number	US-10789168-B2
Application number	US-201815964264-A
Country	US
Kind code	B2
Filing date	Apr 27, 2018
Priority date	Apr 27, 2018
Publication date	Sep 29, 2020
Grant date	Sep 29, 2020

Abstract

Maintaining multiple cache areas in a storage device having multiple processors includes loading data from a specific portion of non-volatile storage into a local cache area in response to a specific processor of a first subset of the processors performing a read operation to the specific portion of non-volatile storage, where the local cache area is accessible to the first subset of the processors and is inaccessible to a second subset of the processors that is different than the first subset of the processors and includes loading data from the specific portion of non-volatile storage into a global cache area in response to one of the processors performing a write operation to the specific portion of non-volatile storage, where the global cache area is accessible to the first subset of the processors and to the second subset of the processors. Different processors may be placed on different directors.

First claim

What is claimed is:

1. A method of maintaining multiple cache areas in a storage device having multiple processors, comprising:
loading data from a specific portion of non-volatile storage into a local cache area in response to a specific processor of a first subset of the processors performing a read operation to the specific portion of non-volatile storage, wherein the local cache area is accessible to the first subset of the processors and is inaccessible to a second subset of the processors that is different than the first subset of the processors;
loading data from the specific portion of non-volatile storage into a global cache area in response to one of the processors performing a write operation to the specific portion of non-volatile storage, wherein the global cache area is accessible to the first subset of the processors and to the second subset of the processors; and
removing specific data from the local cache area and loading the specific data to the global cache area in response to a write operation to the specific data.

2. A method, according to claim 1 , wherein different ones of the processors are placed on different directors.

3. A method, according to claim 2 , wherein the global cache area and the local cache area are provided by memory on the directors.

4. A method, according to claim 3 , wherein a portion of the memory corresponding to the global cache area is accessible to all of the directors.

5. A method, according to claim 3 , wherein a portion of the memory corresponding to the local cache area is only accessible by processors on a same one of the directors as the portion of the memory.

6. A method, according to claim 1 , wherein following loading the data into the local cache area, storage of the data in the global cache area is cancelled.

7. A method, according to claim 1 , further comprising:
loading data from the specific portion of non-volatile storage into the global cache area in response to the specific processor performing a read operation of data meeting other criteria that would cause the data to not be initially loaded into the local cache area.

8. A method, according to claim 7 , wherein the other criteria is that the data needs to be locked.

9. A non-transitory computer readable medium containing software that maintains multiple cache areas in a storage device having multiple processors, the software comprising:
executable code that loads data from a specific portion of non-volatile storage into a local cache area in response to a specific processor of a first subset of the processors performing a read operation to the specific portion of non-volatile storage, wherein the local cache area is accessible to the first subset of the processors and is inaccessible to a second subset of the processors that is different than the first subset of the processors;
executable code that loads data from the specific portion of non-volatile storage into a global cache area in response to one of the processors performing a write operation to the specific portion of non-volatile storage, wherein the global cache area is accessible to the first subset of the processors and to the second subset of the processors; and
executable code that removes specific data from the local cache area and loads the specific data to the global cache area in response to a write operation to the specific data.

10. A non-transitory computer readable medium, according to claim 9 , wherein different ones of the processors are placed on different directors.

11. A non-transitory computer readable medium, according to claim 10 , wherein the global cache area and the local cache area are provided by memory on the directors.

12. A non-transitory computer readable medium, according to claim 11 , wherein a portion of the memory corresponding to the global cache area is accessible to all of the directors.

13. A non-transitory computer readable medium, according to claim 11 , wherein a portion of the memory corresponding to the local cache area is only accessible by processors on a same one of the directors as the portion of the memory.

14. A non-transitory computer readable medium, according to claim 9 , wherein following loading the data into the local cache area, storage of the data in the global cache area is cancelled.

15. A non-transitory computer readable medium, according to claim 9 , the software further comprising:
executable code that loads data from the specific portion of non-volatile storage into the global cache area in response to the specific processor performing a read operation of data meeting other criteria that would cause the data to not be initially loaded into the local cache area.

16. A non-transitory computer readable medium, according to claim 15 , wherein the other criteria is that the data needs to be locked.

Assignees

• Emc Ip Holding Co Llc

Inventors

• Fu Jack
• Li Ningdong
• Scharland Michael J
• Yu Rong

Classifications

• G06F12/084

  with a shared cache · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F12/0811 Primary

  with multilevel cache hierarchies · CPC title

• G06F12/0808

  with cache invalidating means (G06F12/0815 takes precedence) · CPC title

• G06F12/0804

  with main memory updating (G06F12/0806 takes precedence) · CPC title