Systems and methods for scalable hierarchical polyhedral compilation

Patent metadata

Field	Value
Publication number	US-10789055-B2
Application number	US-201615285810-A
Country	US
Kind code	B2
Filing date	Oct 5, 2016
Priority date	Oct 5, 2015
Publication date	Sep 29, 2020
Grant date	Sep 29, 2020

Abstract

A system for compiling programs for execution thereof using a hierarchical processing system having two or more levels of memory hierarchy can perform memory-level-specific optimizations, without exceeding a specified maximum compilation time. To this end, the compiler system employs a polyhedral model and limits the dimensions of a polyhedral program representation that is processed by the compiler at each level using a focalization operator that temporarily reduces one or more dimensions of the polyhedral representation. Semantic correctness is provided via a defocalization operator that can restore all polyhedral dimensions that had been temporarily removed.

First claim

What is claimed is:

1. A method for optimizing execution of a program by a processing system comprising a hierarchical memory having a plurality of memory levels, the method comprising:
(a) for each memory level in at least a subset of memory levels in the plurality of memory levels focalizing a loop dimension of a selected loop nest within a program, the loop nest having a nesting level of N, N being greater than 1, focalizing comprising:
removing an iterator corresponding to a loop index associated with the loop dimension being focalized, reducing the nesting level to N−1;
in the loop nest having the reduced nesting level, at least one of:
(i) removing from a loop condition at another loop dimension of the selected loop nest a subcondition corresponding to the loop index; and
(ii) removing from a memory access expression of an operand, a reference to the loop index; and

storing the loop index and associated focalization information for that memory level; and

(b) for each focalized dimension, defocalizing that dimension by:
adding an iterator based on a reintroduced loop index associated with the loop dimension being defocalized; and
at least one of:
updating a loop condition at another loop dimension of the selected loop nest based on the stored focalization information associated with the loop dimension being defocalized; and
updating the memory access expression of the operand based on the reintroduced loop index and the stored focalization information.

2. The method of claim 1 , further comprising at least one of: (i) tiling the selected loop nest, and (ii) strip mining the selected loop nest, to optimize memory access associated with an operand accessed within the selected loop nest, at that memory level.

3. The method of claim 1 , wherein the focalization information comprises at least one of a loop bound and a tile size.

4. The method of claim 1 , wherein:
a first dimension is focalized at a first memory level; and
a second dimension different from the first dimension is focalized at a second memory level.

5. The method of claim 1 , wherein:
a first dimension is focalized at a first memory level; and
the first dimension is also focalized at a second memory level.

6. The method of claim 5 , wherein:
a first tile size is associated with the first dimension at the first memory level; and
a second tile size different from the first tile size is associated with first dimension at the second memory level.

7. The method of claim 1 , wherein the loop dimension being focalized is at least one of: (i) the outer-most dimension of the selected loop nest, (ii) a dimension in which memory accesses are piecewise uniformly generated references (PUGRs), and (iii) a dimension in which memory accesses are uniformly generated references (UGRs).

8. The method of claim 1 , further comprising performing for at least one memory level at least one loop-nest transformation prior to the focalizing step, the loop-nest transformation being selected from the group consisting of loop fission, loop fusion, loop interchange, loop unroll, loop jam and unroll, loop reversal, strip mining, and loop tiling.

9. The method of claim 1 , wherein a characteristic of memory at a first memory level is different from the characteristic of memory at a second memory level, the characteristic being selected from the group consisting of memory size, memory speed, and memory power consumption.

10. The method of claim 1 , further comprising:
determining that all memory access within a candidate loop nest are PUGRs or UGRs; and
selecting the candidate loop nest as the selected loop nest.

11. The method of claim 1 , further comprising:
generating a set of schedule constraints prior to performing the focalizing step; and
testing a violation of the schedule constraints after at least one defocalization step.

12. A system for facilitating optimized execution of a program by a processing system comprising a hierarchical memory having a plurality of memory levels, the system comprising:
a first processor; and
a first memory in electrical communication with the first processor, the first memory comprising instructions which, when executed by a processing unit comprising at least one of the first processor and a second processor, and in electronic communication with a memory module comprising at least one of the first memory and a second memory, program the processing unit to:
(a) for each memory level in at least a subset of memory levels in the plurality of memory levels, focalize a loop dimension of a selected loop nest within a program, the loop nest having a nesting level of N, N being greater than 1, wherein to focalize the loop dimension the instructions program the processing unit to:
remove an iterator corresponding to a loop index associated with the loop dimension being focalized, reducing the nesting level to N−1;
in the loop nest having the reduced nesting level, at least one of:
(i) remove from a loop condition at another loop dimension of the selected loop nest a subcondition corresponding to the loop index; and
(ii) remove from a memory access expression of an operand, a reference to the loop index; and

store the loop index and associated focalization information for that memory level; and

(b) for each focalized dimension, defocalize that dimension, wherein to defocalize the dimension the instructions program the processing unit to:
add an iterator based on a reintroduced loop index associated with the loop dimension being defocalized; and
at least one of:
update a loop condition at another loop dimension of the selected loop nest based on the stored focalization information associated with the loop dimension being defocalized; and
update the memory access expression of the operand based on the reintroduced loop index and the stored focalization information.

13. The system of claim 12 , wherein the instructions further program the processing unit to, at least one of: (i) tile the selected loop nest, and (ii) strip mine the selected loop nest, to optimize memory access associated with an operand accessed within the selected loop nest, at that memory level.

14. The system of claim 12 , wherein the focalization information comprises at least one of a loop bound and a tile size.

15. The system of claim 12 , wherein the instructions program the processing unit to:
focalize a first dimension at a first memory level; and
focalize a second dimension different from the first dimension at a second memory level.

16. The system of claim 12 , wherein the instructions program the processing unit to:
focalize a first dimension at a first memory level; and
focalize the first dimension also at a second memory level.

17. The system of claim 16 , wherein:
a first tile size is associated with the first dimension at the first memory level; and
a second tile size different from the first tile size is associated with first dimension at the second memory level.

18. The system of claim 12 , wherein the loop dimension being focalized is at least one of: (i) the outer-most dimension of the selected loop nest, (ii) a dimension in which memory accesses are piecewise uniformly generated references (PUGRs), and (iii) a dimension in which memory accesses are uniformly generated references (UGRs).

19. The system of claim 12 , wherein the instructions program the processing unit to perform for at least one memory level at least one loop-nest transformation prior to the focalization operation, the loop-nest transformation being selected f

Assignees

• Reservoir Labs Inc

Inventors

• Baskaran Muthu Manikandan
• Meister Benoit J
• Pradelle Benoit

Classifications

• G06F8/452

  Loops · CPC title

• G06F8/41

  Compilation · CPC title

• G06F8/4436 Primary

  Exlining; Procedural abstraction · CPC title