Lateral heterojunctions between a first layer and a second layer of transition metal dichalcogenide

Patent metadata

Field	Value
Publication number	US-10784353-B2
Application number	US-201716342432-A
Country	US
Kind code	B2
Filing date	Nov 15, 2017
Priority date	Nov 16, 2016
Publication date	Sep 22, 2020
Grant date	Sep 22, 2020

Abstract

A device comprising: at least one first layer, such as a graphene layer, at least one second layer of transition metal dichalcogenide, wherein the at least one first layer and the at least one second layer of transition metal dichalcogenide form at least one heterojunction. The first and second layers are laterally displaced but may overlap over a length of 0 nm to 500 nm. A low-resistance contact is formed. The device can be a transistor including a field effect transistor. The layers can be formed by chemical vapor deposition. The graphene can be heavily p-doped. Transistor performance data are described.

First claim

What is claimed is:

1. A device comprising:
at least one first layer, wherein the first layer has a thickness of 20 nm or less;
at least one second layer, different from the first, which is a transition metal dichalcogenide layer, wherein the second layer has a thickness of 20 nm or less,
wherein the at least one first layer and the at least one second layer form at least one lateral heterojunction, and
wherein the at least one lateral heterojunction is a lateral penetrating heterojunction.

2. The device of claim 1 , wherein the lateral penetrating heterojunction has a penetration length from 1 nm to 500 nm.

3. The device of claim 1 , wherein the lateral heterojunction has an overlapped length from 0 nm to 500 nm.

4. The device of claim 1 , wherein the lateral heterojunction has an overlapped length from 1 nm to 500 nm.

5. The device of claim 1 , wherein the first layer is a graphene layer, a boron nitride layer, a phosphorene layer, or a transition metal dichalcogenide layer that is different from the second layer.

6. The device of claim 1 , wherein the first layer is an un-doped graphene layer, a p-doped graphene layer, or an n-doped graphene layer.

7. The device of claim 1 , wherein the first layer is a p-doped graphene layer or an n-doped graphene layer, and the second layer is a p-type transition metal dichalcogenide or an n-type transition metal dichalcogenide.

8. The device of claim 1 , wherein the device comprises at least two domains for the first layer and each of the two domains are in contact with the second layer of transition metal dichalcogenide to form at least two lateral heterojunctions.

9. The device of claim 1 , wherein the device comprises at least two domains for the first layer and each of the two domains are in contact with the second layer of transition metal dichalcogenide to form at least two lateral interpenetrating heterojunctions.

10. The device of claim 1 , wherein the device comprises at least two domains for the first layer, wherein one of the two domains is in contact with the second layer which is an n-type second layer, and the other of the two domains is in contact with the second layer which is a p-type second layer.

11. The device of claim 1 , wherein the device is a transistor, a photo-sensor, a solar cell, or a light-emitting diode.

12. A method of making a device, the method comprising:
forming at least one first layer on a substrate;
forming at least one second layer, which different from the first layer, the at least one first layer and the at least one second layer forming at least one lateral heterojunction,
wherein the at least one second layer is a transition metal dichalcogenide layer, and
wherein the at least one lateral heterojunction is a lateral penetrating heterojunction.

13. The method of claim 12 , wherein the at least one second layer is formed by chemical vapor deposition or physical vapor deposition, and the at least one first layer is formed by patterning.

14. The method of claim 13 , wherein the formation of at least one first layer by patterning comprises dry etching or wet etching.

15. A semiconductor device, comprising:
a substrate;
a transition metal dichalcogenide layer arranged on the substrate;
a first layer arranged on the substrate, the first layer comprising a first part laterally arranged on a first side of the transition metal dichalcogenide layer and a second part laterally arranged on a second side of the transition metal dichalcogenide layer, wherein the first and second sides of the transition metal dichalcogenide layer are laterally opposite of each other, wherein the first layer and the transition metal dichalcogenide layer form a lateral penetrating heterojunction;
a gate insulator arranged on top of the transition metal dichalcogenide layer and the first layer; and
a top gate arranged on the gate insulator.

16. The semiconductor device of claim 15 , wherein the first layer is a graphene layer, a boron nitride layer, a phosphorene layer, or a further transition metal dichalcogenide layer that is different from the transition metal dichalcogenide layer.

17. The semiconductor device of claim 15 , further comprising:
first and second metal contacts respectively arranged on the first and second parts of the first layer.

18. The semiconductor device of claim 15 , wherein the first layer is an un-doped graphene layer, a p-doped graphene layer, or an n-doped graphene layer.

19. The semiconductor device of claim 15 , wherein the first layer is a p-doped graphene layer or an n-doped graphene layer, and the transition metal dichalcogenide layer is a p-type transition metal dichalcogenide or an n-type transition metal dichalcogenide.

Assignees

• Univ King Abdullah Sci & Tech

Inventors

• Li Lain-Jong
• Tang Hao-Ling
• Chiu Ming-Hui

Classifications

• H10D64/01

  Manufacture or treatment · CPC title

• H10D62/8303

  Diamond · CPC title

• H10D62/882 Primary

  Graphene · CPC title

• H10D62/80

  characterised by the materials · CPC title

• H10D48/362

  Unipolar transistors having ohmic electrodes on emitter-like, base-like, and collector-like regions, e.g. hot electron transistors [HET], metal base transistors [MBT], resonant tunnelling transistors [RTT], bulk barrier transistors [BBT], planar doped barrier transistors [PDBT] or charge injection transistors [CHINT] · CPC title