Display panel having a grading wiring design

Patent metadata

Field	Value
Publication number	US-10784288-B2
Application number	US-201816192827-A
Country	US
Kind code	B2
Filing date	Nov 16, 2018
Priority date	Jun 22, 2018
Publication date	Sep 22, 2020
Grant date	Sep 22, 2020

Abstract

A display panel has a display region, an external circuit region located at an edge of the display panel, and a first and second wiring regions. The first wiring region is located between the second wiring region and the external circuit region. The display panel includes a pixel array, gate driving circuit groups disposed between the second wiring region and the display region, first signal line groups extended from the external circuit region to the first and second wiring region, and second signal line groups extended from the second wiring region and connected to the corresponding gate driving circuit groups. In the second wiring region, a first portion of the first signal line groups overlapped with the second signal line groups has a first width, and a second portion thereof not overlapped with the second signal line groups has a third width which is larger than the first width.

First claim

What is claimed is:

1. A display panel having a display region, a first wiring region, a second wiring region and an external circuit region, wherein the external circuit region located at an edge of the display panel, and the first wiring region disposed between the external circuit region and the second wiring region, the display panel comprising:
a pixel array disposed in the display region;
a plurality of gate driving circuit groups, disposed between the second wiring region and the display region, and the plurality of gate driving circuit groups electrically connected to the pixel array;
a plurality of first signal line groups extended from the external circuit region to the first wiring region and the second wiring region; and
a plurality of second signal line groups extended from the second wiring region and connected to the corresponding plurality of gate driving circuit groups, wherein the plurality of second signal line groups respectively connected to the corresponding plurality of first signal line groups, and the plurality of second signal line groups partially overlapped with the plurality of first signal line groups,
wherein in the second wiring region, a first portion of the plurality of first signal line groups overlapped with the plurality of second signal line groups has a first width and a second portion of the plurality of first signal line groups not overlapped with the plurality of second signal line groups has a third width, wherein the third width is larger than the first width.

2. The display panel according to claim 1 , wherein a current of the first portion of the plurality of first signal line groups is I A , and the plurality of first signal line groups has a second width in the first wiring region, and a current of the plurality of first signal line groups in the first wiring region is I B , a ratio of the first width and the second width is approximately equal to I A 2 /I B 2 .

3. The display panel according to claim 2 , wherein the third width is approximately equal to the second width.

4. The display panel according to claim 1 , wherein the first width between each of the plurality of first signal line groups are different from each other.

5. The display panel according to claim 4 , wherein the first width of one of the plurality of first signal line groups adjacent to the external circuit region is larger than the first width of another one of the plurality of first signal line groups away from the external circuit region.

6. The display panel according to claim 1 , wherein each of the plurality of first signal line groups comprises a plurality of first signal lines, wherein widths of the plurality of first portion of the first signal lines overlapped with the plurality of second signal line groups are the same.

7. The display panel according to claim 1 , wherein the plurality of first signal line groups comprise an initial signal line, a high-frequency signal line, a low-frequency signal line, a low-level signal line, or a constant voltage signal line.

8. A display panel having a display region, a first wiring region, a second wiring region and an external circuit region, wherein the external circuit region located at an edge of the display panel, and the first wiring region located between the external circuit region and the second wiring region, the display panel comprising:
a pixel array disposed in the display region;
a plurality of gate driving circuit groups disposed between the second wiring region and the display region, wherein the plurality of gate driving circuit groups electrically connected to the pixel array;
a plurality of first signal line groups extended from the external circuit region to the first wiring region and the second wiring region; and
a plurality of second signal line groups extended from the second wiring region and connected to the corresponding plurality of gate driving circuit groups, wherein the second signal line groups respectively connected to the corresponding plurality of first signal line groups and the second signal line groups partially overlapped with the plurality of first signal line groups,
wherein a first portion of the plurality of first signal line groups overlapped with the plurality of second signal line groups has a first width, and the plurality of first signal line groups have a second width in the first wiring region, and the first width between each of the plurality of first signal line groups are different from each other.

9. The display panel according to claim 8 , wherein a current of the first portion of the plurality of first signal line groups overlapped with the plurality of second signal line groups is I A , a current of the plurality of first signal line groups in the first wiring region is I B , and a ratio of the first width to the second width is approximately equal to I A 2 /I B 2 .

10. The display panel according to claim 8 , wherein in the second wiring region, a second portion of the plurality of first signal line groups not overlapped with the plurality of second signal line groups has a third width, and the third width is approximately equal to the second width.

11. The display panel according to claim 10 , wherein the third width is larger than the first width.

12. The display panel according to claim 8 , wherein the first width of one of the plurality of first signal line groups adjacent to the external circuit region is larger than the first width of another one of the plurality of first signal line groups away from the external circuit region.

13. The display panel according to claim 8 , wherein each of the plurality of first signal line groups comprises a plurality of first signal lines, wherein widths of the first portion of the plurality of first signal lines overlapped with the plurality of second signal line groups are the same.

14. The display panel according to claim 8 , wherein the plurality of first signal line groups comprise an initial signal line, a high-frequency signal line, a low-frequency signal line, a low-level signal line, or a constant voltage signal line.

Assignees

• Au Optronics Corp

Inventors

• Tung Che-Wei
• Lin Wei-Li
• Cheng Keng-Chuan

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title