Electrostatic discharge protection circuit

Patent metadata

Field	Value
Publication number	US-10784252-B2
Application number	US-201816136566-A
Country	US
Kind code	B2
Filing date	Sep 20, 2018
Priority date	Sep 20, 2018
Publication date	Sep 22, 2020
Grant date	Sep 22, 2020

Abstract

An ESD protection circuit, which protects a subject NMOS transistor coupled between an I/O pad and a ground, includes a first discharge device arranged between the I/O pad and the ground, having a trigger-on voltage that is lower than a breakdown voltage of the subject NMOS transistor; and a gate voltage control device, including a discharge NMOS transistor coupled to the ground and a gate of the subject NMOS transistor; a first PMOS transistor connected to the gate of the subject NMOS transistor and a connection node; and a first NMOS transistor connected to the connection node and the ground. The connection node is connected to the gate of the discharge NMOS transistor, and the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to each other.

First claim

What is claimed is:

1. An electrostatic discharge (ESD) protection circuit, which protects a subject NMOS transistor coupled between an I/O pad and a ground, comprising:
a first discharge device arranged between the I/O pad and the ground, having a trigger-on voltage that is lower than a breakdown voltage of the subject NMOS transistor; and
a gate voltage control device, comprising:
a discharge NMOS transistor coupled to the ground and a gate of the subject NMOS transistor;
a first PMOS transistor connected to the gate of the subject NMOS transistor and a connection node; and
a first NMOS transistor connected to the connection node and the ground;

wherein the connection node is connected to a gate of the discharge NMOS transistor, and a gate of the first PMOS transistor and a gate of the first NMOS transistor are connected to each other;
when an ESD voltage from an ESD event is present at the gate of the subject NMOS transistor, the first PMOS transistor is turned on, and the discharge NMOS transistor is turned on by the ESD voltage to ground the gate of the subject NMOS transistor to ensure that the subject NMOS transistor is turned off.

2. The ESD protection circuit as claimed in claim 1 , further comprising a trace-high circuit which includes:
a second PMOS transistor connected to a power terminal and a first output terminal; and
a third PMOS transistor connected to the gate of the subject NMOS transistor and the first output terminal;
wherein the first output terminal is connected to a body of the first PMOS transistor; a gate of the second PMOS transistor is connected to the gate of the subject NMOS transistor; and a gate of the third PMOS transistor is connected to the power terminal.

3. The ESD protection circuit as claimed in claim 2 , further comprising a voltage clamping circuit which at least includes:
a resistor with a first terminal and a second terminal, wherein the first terminal of the resister is connected to the power terminal and the second terminal of the resister is connected to the gate of the first PMOS transistor; and
a capacitor with a first terminal and a second terminal, wherein the first terminal of the capacitor is directly connected to the second terminal of the resistor, and the second terminal of the capacitor is connected to the ground.

4. The ESD protection circuit as claimed in claim 3 , further comprising a buffer device which includes a buffer or multiple buffers which are connected in series;
wherein an input terminal of the buffer device is connected to the second terminal of the resistor, an output terminal of the buffer device is connected to the gates of the first PMOS transistor and the first NMOS transistor;
wherein a power input terminal of each buffer of the buffer device is connected to the first output terminal of the trace-high circuit.

5. The ESD protection circuit as claimed in claim 4 , further comprising a transmission gate which includes:
a second NMOS transistor connected to a signal terminal and a second output terminal;
a fourth PMOS transistor connected to the signal terminal and the second output terminal; and
an inverter with an input terminal and an output terminal;
wherein the second output terminal is connected to the gate of the subject NMOS transistor; a body of the second NMOS transistor is connected to the ground; a body of the fourth PMOS transistor is connected to the power terminal; a gate of the second NMOS transistor is connected to the input terminal of the inverter and also connected to the gates of the first PMOS transistor and the first NMOS transistor; and a gate of the fourth PMOS transistor is connected to the output terminal of the inverter.

Assignees

• Vanguard Int Semiconduct Corp

Inventors

• Huang Shao-Chang
• Chen li-fan
• Lin Chih-Hsuan
• Wang yu-kai
• Chen Hung-Wei
• Wang Ching-Wen
• Lin Ting-You
• Chen Chun-Chih

Classifications

• H10D89/811 Primary

  using FETs as protective elements · CPC title

• H02H9/046

  responsive to excess voltage appearing at terminals of integrated circuits · CPC title

• H01L27/0266 Primary

  Electricity · mapped topic