Drive circuit, display panel, display device, and method for driving the display panel

Patent metadata

Field	Value
Publication number	US-10783824-B2
Application number	US-201916390538-A
Country	US
Kind code	B2
Filing date	Apr 22, 2019
Priority date	Sep 25, 2018
Publication date	Sep 22, 2020
Grant date	Sep 22, 2020

Abstract

The disclosure discloses a drive circuit, a display panel, a display device, and a method for driving the display panel; wherein the drive circuit includes a plurality of shift register groups including at least one shift register, and a clock signal input sub-circuit; the clock signal input sub-circuit is configured to input clock signals to respective shift registers in the plurality of shift register groups through a plurality of clock signal lines for controlling outputs of the respective shift registers, wherein durations of valid levels of clock signals applied to a same shift register group are same, and durations of valid levels of clock signals applied to different shift register groups are different.

First claim

The invention claimed is:

1. A drive circuit, comprising:
a plurality of shift register groups, each of which comprises at least one shift register;
a plurality of gate lines corresponding to respective shift registers in the plurality of shift register groups in a one-to-one manner;
a plurality of clock signal lines connected with the respective shift registers, wherein a duration of a valid level of a scan signal input to each of the plurality of gate lines is same as durations of valid levels of corresponding clock signals of the plurality of clock signal lines for controlling outputs of the respective shift registers; and
a clock signal input sub-circuit configured to input clock signals to the respective shift registers in the plurality of shift register groups through the plurality of clock signal lines for controlling the outputs of the respective shift registers, wherein durations of valid levels of clock signals applied to a same shift register group are same, and durations of valid levels of clock signals applied to different shift register groups are different;
wherein the clock signal input sub-circuit is configured to increase the durations of the valid levels of the clock signals applied to the different shift register groups successively in a transmission direction of the clock signals on the plurality of clock signal lines.

2. The drive circuit according to claim 1 , wherein the clock signal input sub-circuit is configured to increase the durations of the valid levels of the clock signals applied to the different shift register groups by a same increment successively in the transmission direction of the clock signals on the plurality of clock signal lines.

3. The drive circuit according to claim 1 , wherein numbers of shift registers in respective shift register groups are same.

4. The drive circuit according to claim 1 , wherein the plurality of shift register groups are arranged in an extension direction of the plurality of clock signal lines sequentially.

5. A display panel, comprising a drive circuit, wherein the drive circuit comprises:
a plurality of shift register groups, each of which comprises at least one shift register;
a plurality of gate lines corresponding to respective shift registers in the plurality of shift register groups in a one-to-one manner;
a plurality of clock signal lines connected with the respective shift registers, wherein a duration of a valid level of a scan signal input to each of the plurality of gate lines is same as durations of valid levels of corresponding clock signals of the plurality of clock signal lines for controlling outputs of the respective shift registers; and
a clock signal input sub-circuit configured to input clock signals to the respective shift registers in the plurality of shift register groups through the plurality of clock signal lines for controlling the outputs of the respective shift registers, wherein durations of valid levels of clock signals applied to a same shift register group are same, and durations of valid levels of clock signals applied to different shift register groups are different;
wherein the clock signal input sub-circuit is configured to increase the durations of the valid levels of the clock signals applied to the different shift register groups successively in a transmission direction of the clock signals on the plurality of clock signal lines.

6. The display panel according to claim 5 , wherein the clock signal input sub-circuit is configured to increase the durations of the valid levels of the clock signals applied to the different shift register groups by a same increment successively in the transmission direction of the clock signals on the plurality of clock signal lines.

7. The display panel according to claim 5 , wherein numbers of shift registers in respective shift register groups are same.

8. The display panel according to claim 5 , wherein the plurality of shift register groups are arranged in an extension direction of the plurality of clock signal lines sequentially.

9. A display device, comprising a display panel, the display panel comprises a drive circuit, wherein the drive circuit comprises:
a plurality of shift register groups, each of which comprises at least one shift register;
a plurality of gate lines corresponding to respective shift registers in the plurality of shift register groups in a one-to-one manner;
a plurality of clock signal lines connected with the respective shift registers, wherein a duration of a valid level of a scan signal input to each of the plurality of gate lines is same as durations of valid levels of corresponding clock signals of the plurality of clock signal lines for controlling outputs of the respective shift registers; and
a clock signal input sub-circuit configured to input clock signals to the respective shift registers in the plurality of shift register groups through the plurality of clock signal lines for controlling the outputs of the respective shift registers, wherein durations of valid levels of clock signals applied to a same shift register group are same, and durations of valid levels of clock signals applied to different shift register groups are different;
wherein the clock signal input sub-circuit is configured to increase the durations of the valid levels of the clock signals applied to the different shift register groups successively in a transmission direction of the clock signals on the plurality of clock signal lines.

10. The display device according to claim 9 , wherein the clock signal input sub-circuit is configured to increase the durations of the valid levels of the clock signals applied to the different shift register groups by a same increment successively in the transmission direction of the clock signals on the plurality of clock signal lines.

11. The display device according to claim 9 , wherein numbers of shift registers in respective shift register groups are same.

12. The display device according to claim 9 , wherein the plurality of shift register groups are arranged in an extension direction of the plurality of clock signal lines sequentially.

13. A method for driving the display panel according to claim 5 , wherein the method comprises:
inputting clock signals to the respective shift registers in the plurality of shift register groups through the plurality of clock signal lines for controlling the outputs of the respective shift registers;
wherein durations of valid levels of clock signals applied to a same shift register group are same, and durations of valid levels of clock signals applied to different shift register groups are different;
wherein the durations of the valid levels of the clock signals applied to the different shift register groups increase successively in a transmission direction of the clock signals on the plurality of clock signal lines.

14. The method according to claim 13 , wherein the durations of the valid levels of the clock signals applied to the different shift register groups increase by a same increment successively in the transmission direction of the clock signals on the plurality of clock signal lines.

15. The method according to claim 13 , wherein numbers of shift registers in respective shift register groups are same.

16. The method according to claim 13 , wherein the plurality of shift register groups are arranged in an extension direction of the plurality of clock signal lines sequentially.

Assignees

• Chongqing Boe Optoelectronics Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Hsu Yihjen
• Zhang Xiuqin
• Xiao Lijun
• Gao Shaohong
• Liu Zhiyou
• Zhao Yanan

Classifications

• G09G3/3648

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G3/3225 Primary

  using an active matrix · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title