Simulation methods and systems for predicting SER

Patent metadata

Field	Value
Publication number	US-10783306-B2
Application number	US-201715645227-A
Country	US
Kind code	B2
Filing date	Jul 10, 2017
Priority date	Oct 27, 2016
Publication date	Sep 22, 2020
Grant date	Sep 22, 2020

Abstract

A soft error rate (SER) associated with a design of a semiconductor circuit may be predicted based on implementing a simulation associated with the design. The simulation may include generating a simulation environment based on information indicating the design, performing a particle strike simulation based on the simulation environment to generate charge deposition information, and calculating a collected charge quantity from the charge deposition information. A determination may be made whether the SER predicted based on the collected charge quantity at least meets a threshold. The design may be modified, and the simulation repeated, if the predicted SER value meets a threshold value. A semiconductor circuit may be manufactured based on the design if the predicted SER value is less than the threshold value.

First claim

What is claimed is:

1. A method comprising:
receiving layout and netlist information associated with a design of a semiconductor circuit, the semiconductor circuit including a three-dimensional (3D) semiconductor device;
generating a simulation environment based on the layout and netlist information, the simulation environment including a representation of the semiconductor circuit according to the design of the semiconductor circuit;
determining a sensitive node or a sensitive region according to type or function of the semiconductor circuit based on the layout and netlist information;
performing a particle strike simulation based on the simulation environment to generate charge deposition information associated with the design of the semiconductor circuit;
calculating a collected charge quantity associated with the sensitive node or the sensitive region based on the charge deposition information; and
manufacturing the semiconductor circuit based on the collected charge quantity.

2. The method of claim 1 , wherein,
calculating the collected charge quantity includes measuring a charge quantity at the sensitive node.

3. The method of claim 1 , wherein,
calculating the collected charge quantity includes measuring a charge quantity at the sensitive region.

4. The method of claim 1 , wherein the simulation environment includes front-end-of-line (FEOL) layer information, middle-of-line (MOL) layer information, and/or back-end-of-line (BEOL) layer information.

5. The method of claim 1 , wherein,
the simulation environment includes a first simulation environment and a second simulation environment,
the first simulation environment reflects a process parameter associated with the design of the semiconductor circuit having a first value, and
the second simulation environment reflects the process parameter having a second value different from the first value.

6. The method of claim 1 , wherein the particle strike simulation is performed based on a Monte-Carlo simulation technique.

7. The method of claim 1 , wherein the performing includes setting a position and velocity of simulated alpha particles or neutrons following a Poisson distribution and determining an initial position thereof in the simulation environment.

8. The method of claim 7 , wherein the performing includes
causing the simulated alpha particles or neutrons to strike the representation of the semiconductor circuit, and
calculating an energy distribution after the strike.

9. The method of claim 1 , wherein the calculating includes
calculating a first deposited charge quantity associated with a drain node of the semiconductor circuit based on the charge deposition information,
calculating a second deposited charge quantity associated with a source node of the semiconductor circuit based on the charge deposition information, and
calculating the collected charge quantity based on the first deposited charge quantity and the second deposited charge quantity.

10. The method of claim 1 , wherein the semiconductor device includes a FinFET semiconductor device, a nanowire semiconductor device, and/or a nanosheet semiconductor device.

11. The method of claim 1 , further comprising:
receiving the layout and netlist information and the simulation environment;
generating a Simulation Program Integrated Circuit Emphasis (SPICE) netlist;
generating ionization current information; and
performing a SPICE simulation based on the SPICE netlist and the ionization current information to estimate a Failure-In-Time (FIT) associated with the design of the semiconductor circuit.

12. A method, comprising:
receiving layout and netlist information indicating a design of a semiconductor circuit, the semiconductor circuit including a three-dimensional (3D) semiconductor device;
generating a simulation environment based on the layout and netlist information, the simulation environment including a representation of the semiconductor circuit;
determining a sensitive node or a sensitive region according to type or function of the semiconductor circuit based on the layout and netlist information;
performing a particle strike simulation based on the simulation environment to determine a soft error rate (SER) involving the sensitive node or the sensitive region; and
manufacturing the semiconductor circuit according to the design of the semiconductor circuit, based on a determination that the SER is less than a threshold value.

13. The method of claim 12 , wherein
determining the SER includes measuring a charge quantity at one of the sensitive node or the sensitive region.

14. The method of claim 12 , wherein,
the simulation environment includes a first simulation environment and a second simulation environment,
the first simulation environment reflects a process parameter associated with the design of the semiconductor circuit having a first value, and
the second simulation environment reflects the process parameter having a second value different from the first value.

15. The method of claim 12 , wherein the performing includes setting a position and velocity of simulated alpha particles or neutrons following a Poisson distribution and determining an initial position thereof in the simulation environment.

16. The method of claim 15 , wherein the performing includes
causing the simulated alpha particles or neutrons to strike the representation of the semiconductor circuit, and
calculating an energy distribution after the strike.

17. A method, comprising:
receiving layout and netlist information indicating a design of a semiconductor circuit, the semiconductor circuit including a three-dimensional (3D) semiconductor device;
generating a simulation environment based on the layout and netlist information, the simulation environment including a representation of the semiconductor circuit;
determining a sensitive node or a sensitive region according to type or function of the semiconductor circuit based on the layout and netlist information;
performing a particle strike simulation based on the simulation environment to determine a soft error rate (SER) involving the sensitive node or the sensitive region;
modifying the design of the semiconductor circuit to establish a modified design, and generating information indicating the modified design, based on a determination that the SER at least meets a threshold value;
implementing the generating and the performing, based on the information indicating the modified design, to determine a SER associated with the modified design; and
manufacturing the semiconductor circuit according to the modified design, based on a determination that the SER associated with the modified design is less than the threshold value.

18. The method of claim 17 , wherein,
the modifying includes adjusting a value of one or more process parameters, process variation values, and/or dimensional parameters associated with one or more structural elements of the semiconductor circuit in the design.

19. The method of claim 17 , wherein,
determining the SER includes measuring a charge quantity at one of the sensitive node or the sensitive region.

20. The method of claim 17 , wherein the performing includes setting a position and velocity of simulated alpha particles or neutrons following a Poisson distribution and determining an initial position thereof in the simulation environment.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Monga Udit
• Jeon Jong Wook
• Machida Ken
• Kwon Ui Hui

Classifications

• H10W42/60

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10W42/25

  against alpha rays, e.g. for outer space applications · CPC title

• H10D62/119

  Nanowire, nanosheet or nanotube semiconductor bodies · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D84/834

  comprising FinFETs · CPC title