Circuit design system, checking method, and non-transitory computer readable medium thereof

Patent metadata

Field	Value
Publication number	US-10783293-B2
Application number	US-201816132804-A
Country	US
Kind code	B2
Filing date	Sep 17, 2018
Priority date	Apr 27, 2018
Publication date	Sep 22, 2020
Grant date	Sep 22, 2020

Abstract

A checking method for checking whether a signal in a chip is interference-free, and the checking method includes the following operations: analyzing, by a processor, a netlist file to acquire a first node for outputting the signal in the chip, in which the netlist file is configured to describe a circuit architecture of the chip; searching, by the processor, candidate nodes associated with the signal according to the netlist file and the first node; and determining, by the processor, whether a first candidate node of the candidate nodes is connected to an anti-interference circuit, in order to check whether the signal is interference-free.

First claim

What is claimed is:

1. A circuit design system, comprising:
a memory configured to store a plurality of program codes; and
a processor configured to execute the plurality of program codes to:
analyze a netlist file to acquire a first node for outputting a signal in a chip to which the netlist file corresponds;
exclude at least one power node and at least one ground node in the netlist file so as to search a plurality of candidate nodes associated with the signal according to the netlist file and the first node; and
determine whether a first candidate node of the plurality of candidate nodes is connected to an anti-interference circuit, in order to check whether the signal is interference-free,
wherein the processor is further configured to determine whether the signal is not interference-free, wherein if the processor determines that the signal is not interference-free, the processor outputs a summary report regarding the anti-interference circuit.

2. The circuit design system of claim 1 , wherein the processor is configured to analyze the netlist file to trace back from the first node to at least one partial circuit associated with the signal in the chip, in order to search the plurality of candidate nodes associated with the signal.

3. The circuit design system of claim 2 , wherein the plurality of candidate nodes are coupled to the first node.

4. The circuit design system of claim 2 , wherein the at least one partial circuit excludes the at least one power node and the at least one ground node in the chip.

5. The circuit design system of claim 1 , wherein the processor is configured to sequentially check the plurality of candidate nodes based on a circuit architecture of the anti-interference circuit, in order to check whether the first candidate node is connected to the anti-interference circuit.

6. The circuit design system of claim 1 , wherein the anti-interference circuit comprises a first flip-flop and a second flip-flop, and to check whether the first candidate node is connected to the anti-interference circuit, the processor is configured to:
check whether the first candidate node is connected to an output terminal of the second flip-flop according to the netlist file;
check whether an input terminal of the second flip-flop is coupled to an output terminal of the first flip-flop according to the netlist file if the first candidate node is connected to the output terminal of the second flip-flop; and
determine that the signal is interference-free if the input terminal of the second flip-flop is connected to the output terminal of the first flip-flop.

7. The circuit design system of claim 6 , wherein if the first candidate node is not connected to the output terminal of the second flip-flop or if the input terminal of the second flip-flop is not connected to the output terminal of the first flip-flop, the processor is configured to determine that the signal is not interference-free.

8. The circuit design system of claim 1 , wherein the signal is a clock signal.

9. A checking method for checking whether a signal in a chip is interference-free, the checking method comprising:
analyzing, by a processor, a netlist file to acquire a first node for outputting the signal in the chip, wherein the netlist file is configured to describe a circuit architecture of the chip;
excluding at least one power node and at least one ground node in the netlist file so as to search, by the processor, a plurality of candidate nodes associated with the signal according to the netlist file and the first node;
determining, by the processor, whether a first candidate node of the plurality of candidate nodes is connected to an anti-interference circuit, in order to check whether the signal is interference-free;
determining, by the processor, whether the signal is not interference-free; and
outputting, by the processor, a summary report regarding the anti-interference circuit if the processor determines that the signal is not interference-free.

10. The checking method of claim 9 , wherein the anti-interference circuit comprises a first flip-flop and a second flip-flop, and determining whether the first candidate node is connected to the anti-interference circuit comprises:
checking whether the first candidate node is connected to an output terminal of the second flip-flop according to the netlist file;
checking whether an input terminal of the second flip-flop is coupled to an output terminal of the first flip-flop according to the netlist file if the first candidate node is connected to the output terminal of the second flip-flop; and
determining that the signal is interference-free if the input terminal of the second flip-flop is connected to the output terminal of the first flip-flop.

11. The checking method of claim 10 , wherein if the first candidate node is not connected to the output terminal of the second flip-flop or if the input terminal of the second flip-flop is not connected to the output terminal of the first flip-flop, determining that the signal is not interference free.

12. The checking method of claim 9 , wherein searching the plurality of candidate nodes comprises:
analyzing the netlist file to trace back from the first node to at least one partial circuit associated with the signal in the chip, in order to search the plurality of candidate nodes associated with the signal.

13. The checking method of claim 12 , wherein the plurality of candidate nodes are coupled to the first node.

14. The checking method of claim 12 , wherein the at least one partial circuit excludes the at least one power node and the at least one ground node in the chip.

15. The checking method of claim 9 , wherein determining whether the first candidate node is connected to the anti-interference circuit comprises:
sequentially checking the plurality of candidate nodes based on a circuit architecture of the anti-interference circuit, in order to check whether the first candidate node is connected to the anti-interference circuit.

16. A non-transitory computer readable medium having a computer program which, when executed by a processor, result in the processor performing a plurality of operations comprising:
analyzing a netlist file to acquire a first node for outputting a signal in a chip to which the netlist file corresponds;
excluding at least one power node and at least one ground node in the netlist file so as to search a plurality of candidate nodes associated with the signal according to the netlist file and the first node;
determining whether a first candidate node of the plurality of candidate nodes is connected to an anti-interference circuit, in order to check whether the signal is interference-free;
determining whether the signal is not interference-free; and
outputting a summary report regarding the anti-interference circuit if it is determined that the signal is not interference-free.

17. The non-transitory computer readable medium of claim 16 , wherein searching the plurality of candidate nodes comprises:
analyzing the netlist file to trace back from the first node to at least one partial circuit associated with the signal in the chip, in order to search the plurality of candidate nodes associated with the signal.

18. The non-transitory computer readable medium of claim 17 , wherein the plurality of candidate nodes are coupled to the first node, and the partial circuit excludes the at least one power node and the at least one ground node in the chip.

19. The non-transitory computer readable medium of claim 17 , wherein the ant

Assignees

• Realtek Semiconductor Corp

Inventors

• Kao Shu-Yi
• Lo Yu-Lan
• Lee Meng-Jung
• Lin Yun-Jing

Classifications

• G06F2119/10

  Noise analysis or noise optimisation · CPC title

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title