Image sensor and a method for read-out of pixel signal

Patent metadata

Field	Value
Publication number	US-10778926-B2
Application number	US-201916458641-A
Country	US
Kind code	B2
Filing date	Jul 1, 2019
Priority date	Jul 11, 2018
Publication date	Sep 15, 2020
Grant date	Sep 15, 2020

Abstract

Example embodiments relate to an image sensor and a method for read-out of pixel signal. One embodiment includes an image sensor. The image sensor includes an array of pixels for detecting light incident on the pixel. The image sensor also includes an in-pixel correlated double sampling (CDS) circuitry. The image sensor also includes a column line that extends along and is associated with a column of pixels in the array of pixels. The column line is configured to selectively receive a pixel signal from a pixel in the column. Further, the image sensor includes a voltage-drop correction line that extends along and is associated with the column of pixels. The voltage-drop correction line is configured to provide a correction voltage signal to a pixel in the column such that corrects for voltage drop of the pixel signal in read-out through the column line.

First claim

What is claimed is:

1. An image sensor, comprising:
an array of pixels for detecting light incident on the pixel,
wherein each pixel in the array comprises:
a photodetector for generating a photointegrated signal corresponding to an amount of light incident on the photodetector; and
an in-pixel correlated double sampling (CDS) circuitry, wherein the in-pixel CDS circuitry is connected to the photodetector and is configured to output a CDS signal representative of a difference between the photointegrated signal and a reset signal;

a column line,
wherein the column line extends along and is associated with a column of pixels in the array of pixels, and
wherein the column line is configured to selectively receive a pixel signal from a pixel in the column for reading out a value indicative of the amount of light incident on the photodetector of the pixel; and
a voltage-drop correction line,
wherein the voltage-drop correction line extends along and is associated with the column of pixels, and
wherein the voltage-drop correction line is configured to provide a correction voltage signal to a pixel in the column such that the correction voltage signal is added to the CDS signal for forming the pixel signal from the pixel received by the column line and corrects for voltage drop of the pixel signal in read-out through the column line.

2. The image sensor according to claim 1 ,
wherein each pixel comprises a storage capacitor, and
wherein the storage capacitor is connected to the CDS circuitry and is configured to store the CDS signal.

3. The image sensor according to claim 2 ,
wherein each pixel further comprises a sample switching transistor, and
wherein the sample switching transistor is configured to selectively connect a plate of the storage capacitor to ground.

4. The image sensor according to claim 3 , wherein the sample switching transistor is connected to a sample control line for receiving a sample control signal to activate the sample switching transistor and connect the storage capacitor to ground during integration of light incident on the photodetector for storing the CDS signal.

5. The image sensor according to claim 2 ,
wherein each pixel further comprises a read-out switching transistor, and
wherein the read-out switching transistor is configured to selectively connect a plate of the storage capacitor to the voltage-drop correction line.

6. The image sensor according to claim 5 , wherein the read-out switching transistor is connected to a read-out control line for receiving a read-out control signal to activate the read-out switching transistor and connect the storage capacitor to the voltage-drop correction line during read-out of the pixel signal for adding the correction voltage signal to the CDS signal.

7. The image sensor according to claim 1 , wherein the column line and the voltage-drop correction line are formed as identical lines along the column of pixels.

8. The image sensor according to claim 1 ,
wherein the column line is associated with a column-line current source for providing a bias current on the column line, and
wherein the voltage-drop correction line is associated with a voltage-drop correction current source for providing a bias current on the voltage-drop correction line.

9. The image sensor according to claim 8 , wherein the column-line current source and the voltage-drop correction current source are configured to provide equal bias currents on the column line and the voltage-drop correction line.

10. The image sensor according to claim 8 ,
wherein the voltage-drop correction current source is configured to be controlled to provide a bias current that is larger than the bias current provided by the column-line current source, and
wherein the voltage-drop correction current source is controlled based on a calibration value to compensate for a gain of a source follower for reading out the pixel signal to the column line being lower than 1.

11. The image sensor according to claim 8 , wherein the column-line current source and the voltage-drop correction current source are arranged at a common side in relation to the column of pixels.

12. The image sensor according to claim 1 ,
wherein the array of pixels comprises a plurality of columns, and
wherein the image sensor further comprises a plurality of column lines and voltage-drop correction lines such that one column line and one voltage-drop correction line are associated with each column of pixels.

13. A method for read-out of a pixel signal representative of a detected amount of light from a pixel in an array of pixels, comprising:
generating a photointegrated signal representative of an amount of light incident on a photodetector of the pixel during a sampling period;
forming a correlated double sampling (CDS) signal representative of a difference between the photointegrated signal and a reset signal;
storing the CDS signal in the pixel;
adding a correction voltage signal to the CDS signal for forming the pixel signal,
wherein the correction voltage signal is provided to the pixel from a voltage-drop correction line, and
wherein the voltage-drop correction line extends along a column of pixels in the array; and
reading out the pixel signal to a column line,
wherein the column line extends along the column of pixels, and
wherein the correction voltage signal corrects for voltage drop of the pixel signal in read-out through the column line.

14. The method according to claim 13 , further comprising providing a sample control signal to selectively activate a sample switching transistor to connect a storage capacitor to ground during integration of light incident on the photodetector for storing the CDS signal on the storage capacitor.

15. The method according to claim 14 , further comprising providing a read-out control signal to selectively activate a read-out switching transistor to connect the storage capacitor to the voltage-drop correction line during read-out of the pixel signal for adding the correction voltage signal to the CDS signal.

Assignees

• Imec Vzw

Inventors

• Spagnolo Annachiara
• Borremans Jonathan

Classifications

• H04N25/673 Primary

  by using reference sources · CPC title

• H04N25/616 Primary

  involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling · CPC title

• H04N25/677

  for reducing the column or line fixed pattern noise · CPC title

• H04N25/77

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title