Level shifting in a GaN half bridge circuit

Patent metadata

Field	Value
Publication number	US-10778219-B2
Application number	US-201916554602-A
Country	US
Kind code	B2
Filing date	Aug 28, 2019
Priority date	Nov 15, 2017
Publication date	Sep 15, 2020
Grant date	Sep 15, 2020

Abstract

A half bridge GaN circuit is disclosed. The half bridge GaN circuit includes a first power node having a first power voltage, where the first power voltage is referenced to a switch voltage at the switch node. The half bridge GaN circuit also includes a VMID power node having a VMID power voltage, where the VMID power voltage is referenced to the first power voltage and is less than the first power voltage by a DC voltage. The half bridge GaN circuit also includes a logic circuit, where a negative power terminal of the logic circuit is connected to the VMID node, and where a positive power terminal of the first logic circuit is connected to the first power node, where the logic circuit is configured to generate a logic output voltage, which controls the conductivity of the high side power switch.

First claim

What is claimed is:

1. A half bridge circuit, comprising:
a switch node;
a low side power switch configured to selectively conduct current from the switch node according to one or more input signals;
a high side power switch configured to selectively conduct current to the switch node according to the one or more input signals;
a first power node having a first power voltage, wherein the first power voltage is referenced to a switch voltage at the switch node;
a particular power node having a particular power voltage, wherein the particular power voltage is referenced to the first power voltage and is less than the first power voltage by a DC voltage;
a first logic circuit, wherein a negative power terminal of the first logic circuit is connected to the particular power node, and wherein a positive power terminal of the first logic circuit is connected to the first power node, wherein the first logic circuit is configured to generate a first logic output voltage, which controls a conductivity of the high side power switch; and
a second logic circuit, wherein a negative power terminal of the second logic circuit is connected to the switch node, and wherein a positive power terminal of the second logic circuit is connected to the first power node, wherein the second logic circuit is configured to generate a second logic output voltage, which controls the conductivity of the high side power switch.

2. The half bridge circuit of claim 1 , further comprising a control level shift circuit comprising a level shift transistor, wherein the control level shift circuit is configured to cause the first logic circuit to cause the high side power switch to be conductive by generating a level shift signal, wherein a temperature dependence of a voltage of the level shift signal is dominated by a temperature dependence of a gate to source threshold voltage of the level shift transistor,
wherein the first logic circuit controls the conductivity of the high side power switch based on the level shift signal, wherein the first logic circuit comprises a logic circuit transistor, and wherein the first logic circuit has a logic input threshold having a temperature dependence which is dominated by a temperature dependence of a gate to source threshold of the first logic circuit.

3. The half bridge circuit of claim 2 , further comprising a resistor connected to a source of the level shift transistor, wherein a current conducted from the level shift transistor to the resistor is less than about 50% of a current which would be conducted from the level shift transistor to the resistor under a condition that an electrical resistance of the resistor were zero.

4. The half bridge circuit of claim 1 , further comprising:
a semiconductor substrate, wherein the first logic circuit is integrated on the semiconductor substrate, and
wherein the DC voltage is generated by a voltage generator which is not formed on the semiconductor substrate.

5. The half bridge circuit of claim 4 , further comprising:
a Vdd generator, configured to generate a Vdd voltage at a Vdd power node, wherein the Vdd generator is configured to receive the DC voltage and to generate the Vdd voltage based on the DC voltage.

6. The half bridge circuit of claim 1 , further comprising:
a particular voltage generator configured to receive the DC voltage referenced to the switch voltage and to generate the particular power voltage based on the DC voltage.

7. The half bridge circuit of claim 6 , wherein the particular power voltage is substantially equal to the first power voltage minus the DC voltage.

8. The half bridge circuit of claim 6 , wherein the particular power voltage is substantially equal to the first power voltage minus the DC voltage minus a gate to source threshold voltage of a transistor of the particular voltage generator.

9. The half bridge circuit of claim 6 , wherein the particular voltage generator comprises a level shift circuit comprising a level shift transistor, wherein the level shift circuit is configured to receive an input voltage and generate an output voltage substantially equal to the first power voltage minus the input voltage minus a gate to source threshold voltage of the level shift circuit.

10. The half bridge circuit of claim 9 , wherein the particular voltage generator further comprises a source follower circuit configured to generate the particular power voltage.

11. A method of using a GaN half bridge circuit, comprising:
a switch node,
a low side power switch,
a high side power switch,
a first power node having a first power voltage, wherein the first power voltage is referenced to a switch voltage at the switch node,
a particular power node having a particular power voltage, wherein the particular power voltage is referenced to the first power voltage and is less than the first power voltage by a DC voltage,
a first logic circuit, wherein a negative power terminal of the first logic circuit is connected to the particular power node, and wherein a positive power terminal of the first logic circuit is connected to the first power node, and
a second logic circuit, wherein a negative power terminal of the second logic circuit is connected to the switch node, and wherein a positive power terminal of the second logic circuit is connected to the first power node,
wherein the method comprises:
with the low side power switch, selectively conducting current from the switch node according to one or more input signals;
with the high side power switch, selectively conducting current to the switch node according to the one or more input signals;
with the first logic circuit, generating a logic output voltage, which controls a conductivity of the high side power switch; and
with the second logic circuit, generating a second logic output voltage, which controls the conductivity of the high side power switch.

12. The method of claim 11 , wherein the half bridge GaN circuit further comprises a control level shift circuit having a level shift transistor, and wherein the method further comprises:
with the control level shift circuit, causing the first logic circuit to cause the high side power switch to be conductive by generating a level shift signal, wherein a temperature dependence of a voltage of the level shift signal is dominated by a temperature dependence of a gate to source threshold voltage of the level shift transistor; and
with the first logic circuit, controlling the conductivity of the high side power switch based on the level shift signal, wherein the first logic circuit comprises a logic circuit transistor, and wherein the first logic circuit has a logic input threshold having a temperature dependence which is dominated by a temperature dependence of a gate to source threshold of the first logic circuit.

13. The method of claim 12 , wherein the half bridge GaN circuit further comprises a resistor connected to a source of the level shift transistor, wherein a current conducted from the level shift transistor to the resistor is less than about 50% of a current which would be conducted from the level shift transistor to the resistor under a condition that an electrical resistance of the resistor were zero.

14. The method of claim 11 , wherein the half bridge GaN circuit further comprises:
a semiconductor substrate, wherein the first logic circuit is integrated on the semiconductor substrate, and
with a voltage generator which is not formed on the semiconductor substrate, generating the DC voltage.

15. The method of claim 14 , wherein the half bridge GaN circuit further comprises a Vdd generator, and wherein the method fu

Assignees

• Navitas Semiconductor Inc

Inventors

• Sharma Santosh
• Giandalia Marco
• Kinzer Daniel Marvin
• Ribarich Thomas

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07554

  changes in dispositions · CPC title

• H03K2217/0063

  High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load · CPC title