Semiconductor device

Patent metadata

Field	Value
Publication number	US-10777550-B2
Application number	US-201616465537-A
Country	US
Kind code	B2
Filing date	Dec 16, 2016
Priority date	Dec 16, 2016
Publication date	Sep 15, 2020
Grant date	Sep 15, 2020

Abstract

A plurality of gate finger electrodes (2) is each arranged in a manner alternately adjacent to a corresponding one of drain electrodes (3) and a corresponding one of source electrode (4). The plurality of gate finger electrodes (2) is each connected to a corresponding one of gate routing lines (6). A resistor (7) has one end separating the gate routing lines (6) on respective two sides at a center portion between the gate routing lines (6), and has another end connected to an input line (10). Capacitors (8) are arranged on the respective two sides with respect to the resistor (7) and each connected to the corresponding gate routing line (6) by a corresponding one of air bridges (9).

First claim

The invention claimed is:

1. A semiconductor device comprising:
a plurality of gate finger electrodes which is aligned in one direction, and each of which is arranged in a manner alternately adjacent to a corresponding one of drain electrodes and a corresponding one of source electrodes;
gate routing lines provided along the direction in which the plurality of gate finger electrodes is aligned, each of the plurality of gate finger electrodes being connected to a corresponding one of the gate routing lines;
a first resistor having one end separating the gate routing lines on respective two sides at a center portion between the gate routing lines, and having another end connected to an input line;
capacitors arranged on the respective two sides with respect to the first resistor; and
first air bridges provided along the respective gate routing lines and connecting the capacitors to the respective gate routing lines.

2. The semiconductor device according to claim 1 , wherein each of the capacitors has a shape in which a rectangle shape is partially removed.

3. The semiconductor device according to claim 1 , further comprising:
external electrodes in each of which a via is formed; and
second air bridges each connecting a corresponding one of the source electrodes to a corresponding one of the external electrodes.

4. The semiconductor device according to claim 1 , wherein each of the gate routing lines includes a second resistor in a portion corresponding to that between any adjacent two of the gate finger electrodes.

5. A semiconductor device comprising:
a plurality of gate finger electrodes which is aligned in one direction, and each of which is arranged in a manner alternately adjacent to a corresponding one of drain electrodes and a corresponding one of source electrodes;
gate routing lines provided along the direction in which the plurality of gate finger electrodes is aligned, each of the plurality of gate finger electrodes being connected to a corresponding one of the gate routing lines;
a first resistor having one end separating the gate routing lines on respective two sides at a center portion between the gate routing lines, and having another end connected to an input line;
capacitors arranged on the respective two sides with respect to the first resistor; and
a plurality of third air bridges provided in a manner corresponding to the respective plurality of gate finger electrodes, and connecting the capacitors to the respective gate routing lines.

6. The semiconductor device according to claim 5 , wherein
each of the gate routing lines includes a second resistor in a portion corresponding to that between any adjacent two of the gate finger electrodes, and
each of the plurality of third air bridges is connected to a corresponding portion of the gate routing lines, the portion being located between any adjacent two of the second resistors.

Assignees

• Mitsubishi Electric Corp

Inventors

• Yamaguchi Yutaro
• Hangai Masatake
• Yamanaka Koji

Classifications

• H10W20/483

  Interconnections over air gaps, e.g. air bridges · CPC title

• H10W44/234

  Arrangements for impedance matching · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W20/484

  Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes · CPC title

• H10D64/411

  for FETs · CPC title