Techniques for optimizing dual track routing

US10776553B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10776553-B2
Application numberUS-201816004958-A
CountryUS
Kind codeB2
Filing dateJun 11, 2018
Priority dateNov 6, 2013
Publication dateSep 15, 2020
Grant dateSep 15, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The subject technology provides a method and apparatus for performing dual track routing. A pair of signal traces is routed in between two rows of contacts and at least one of the signal traces is modified to satisfy a routing restriction. The modification of the signal trace includes three trace segments that deviate the signal trace away from the source of the routing restriction.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for routing signal traces comprising: routing a first signal trace and a second signal trace on substantially parallel conductive paths; determining the first signal trace violates a routing restriction with a first distance requirement from a drilling location on a printed circuit board and a second distance requirement based on a back-drill bit size associated with the drilling location, wherein the first distance requirement is a minimum distance from the first signal trace to a perimeter of a via at the drilling location and the second distance requirement is a minimum distance from the first signal trace to a perimeter of the back-drill bit size of a drill bit for creating the via; modifying the first signal trace so it satisfies the routing restriction by replacing one or more sections of the first signal trace with at least one serpentine structure, the at least one serpentine structure including: a first trace segment directed towards the second signal trace and away from the drilling location, a second trace segment connected to the first trace segment, the second trace segment being substantially parallel to the second signal trace and extending past the drilling location, and a third trace segment connected to the second trace segment, the third trace segment directed away from the second signal trace. 2. The method of claim 1 , wherein the first signal trace is associated with a signal trace width. 3. The method of claim 2 , wherein the modifying includes reducing a width dimension of at least one of the first trace segment, the second trace segment, or the third trace segment so the width dimension is less than the signal trace width. 4. The method of claim 1 , wherein the substantially parallel conductive paths are located in between two adjacent strings of contacts on an outer layer of the printed circuit board. 5. The method of claim 4 , wherein the two adjacent strings of contacts on the printed circuit board are part of an array of contacts corresponding to an integrated circuit having a ball grid array (BGA) package. 6. The method of claim 1 , wherein the first signal trace and the second signal trace are used for conducting a differential signal pair. 7. The method of claim 1 , wherein a first angle exists between the first trace segment and a line corresponding to the replaced one or more sections and a second angle exists between the third trace segment and the line corresponding to the replaced one or more sections. 8. The method of claim 7 , wherein the first angle and the second angle are substantially equivalent. 9. The method of claim 8 , wherein the first trace segment and the third trace segment are substantially equivalent in length. 10. The method of claim 1 , wherein the substantially parallel conductive paths are located along a string of contacts extending along the printed circuit board. 11. The method of claim 10 , wherein the substantially parallel conductive paths extend substantially parallel to the string of contacts. 12. The method of claim 10 , wherein the first signal trace and the second signal trace extend substantially parallel in a first direction along the printed circuit board and away from the string of contacts before sending in a second direction along the printed circuit board and substantially parallel to the string of contacts. 13. The method of claim 12 , wherein first signal trace extends further in the first direction than the second signal trace. 14. The method of claim 2 , wherein the modifying includes reducing a width dimension of at least the first trace segment so the width dimension is less than the signal trace width. 15. The method of claim 2 , wherein the modifying includes reducing a width dimension of only the first trace segment so the width dimension is less than the signal trace width. 16. The method of claim 2 , wherein the modifying includes reducing a width dimension of only the second trace segment so the width dimension is less than the signal trace width. 17. The method of claim 2 , wherein the modifying includes reducing a width dimension of only the third trace segment so the width dimension is less than the signal trace width. 18. The method of claim 2 , wherein the modifying includes reducing a width dimension of the first trace segment, the second trace segment, and the third trace segment so the width dimension is less than the signal trace width.

Assignees

Inventors

Classifications

  • Natural convection · CPC title

  • Natural convection of gaseous coolant; Heat transfer by conduction from electronic boards · CPC title

  • Via connections; Lands around holes or via connections (H05K1/112 takes precedence) · CPC title

  • G06F30/394Primary

    Routing (G06F30/396 takes precedence) · CPC title

  • Lever acting on a connector mounted onto the flexible or rigid printed circuit boards, flat or ribbon cables · CPC title

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Frequently asked questions

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What does patent US10776553B2 cover?
The subject technology provides a method and apparatus for performing dual track routing. A pair of signal traces is routed in between two rows of contacts and at least one of the signal traces is modified to satisfy a routing restriction. The modification of the signal trace includes three trace segments that deviate the signal trace away from the source of the routing restriction.
Who is the assignee on this patent?
Cisco Tech Inc
What technology area does this patent fall under?
Primary CPC classification H05K7/20127. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 15 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).