Apparatus and method for protecting program memory for processing cores in a multi-core integrated circuit

Patent metadata

Field	Value
Publication number	US-10776292-B2
Application number	US-201916250274-A
Country	US
Kind code	B2
Filing date	Jan 17, 2019
Priority date	Apr 30, 2015
Publication date	Sep 15, 2020
Grant date	Sep 15, 2020

Abstract

An integrated circuit has a master processing core with a central processing unit coupled with a non-volatile memory and a slave processing core operating independently from the master processing core and having a central processing unit coupled with volatile program memory, wherein the master central processing unit is configured to transfer program instructions into the non-volatile memory of the slave processing core and wherein a transfer of the program instructions is performed by executing a dedicated instruction within the central processing unit of the master processing core.

First claim

The invention claimed is:

1. An integrated circuit comprising:
a master processing core having a central processing unit coupled with a non-volatile program memory;
a slave processing core operating independently from the master processing core and having a central processing unit coupled with volatile program memory, wherein a program instruction length of program instructions processed by the slave processing core is larger than an internal data bus length of the master processing core;
wherein the central processing unit of the master processing core is configured to transfer program instructions into the volatile program memory of the slave processing core; and
wherein a transfer of said program instructions is performed by executing a dedicated instruction within the central processing unit of the master processing core that causes a program instruction for the slave processing core to be transferred into the volatile program memory.

2. The integrated circuit according to claim 1 , wherein the dedicated instruction has a first operand defining a source address and a second operand defining a destination address, wherein the destination address is auto-incremented after execution of the dedicated instruction.

3. The integrated circuit according to claim 1 , wherein the dedicated instruction causes an instruction word to be transferred into a buffer, and further causes the instruction word to be written into the volatile program memory from the buffer.

4. The integrated circuit according to claim 3 , wherein the instruction causes the non-volatile program memory to output said instruction word whereupon said information is captured by said buffer.

5. The integrated circuit according to claim 3 , wherein the instruction word is a 24 bit word and said data length is 16 bit.

6. The integrated circuit according to claim 2 , wherein the integrated circuit comprises a plurality of slave processing cores and the dedicated instruction has a third operand defining a target slave processing unit.

7. The integrated circuit according to claim 2 , wherein the source address stored in the first operand can optionally be auto-incremented after execution of the dedicated instruction.

8. The integrated circuit according to claim 2 , wherein the source address is stored in a special function register of a peripheral device associated with the master processing core.

9. The integrated circuit according to claim 8 , wherein the peripheral device is a serial communication peripheral.

10. The integrated circuit according to claim 8 , wherein the peripheral device is a parallel input port.

11. The integrated circuit according to claim 3 , wherein the master processing core is further operable to execute a further instruction that verifies an instruction word that has been transferred into the volatile program memory.

12. The integrated circuit according to claim 11 , wherein the further instruction causes a first instruction word to be transferred into the buffer and wherein the content of the buffer is compared with a second instruction word stored in the volatile program memory.

13. The integrated circuit according to claim 12 , wherein the further instruction comprises a first address which is applied to the non-volatile program memory of the master processing core to output the first instruction word and a second address which is applied to the volatile program memory to output the second instruction word.

14. The integrated circuit according to claim 12 , wherein the further instruction further verifies error correcting code (ECC) associated with the first and second instruction word.

15. The integrated circuit according to claim 14 , wherein the ECC associated with the non-volatile program memory can be read from the non-volatile program memory and the ECC associated with a source is separately generated.

16. The integrated circuit according to claim 1 , wherein the non-volatile program memory of the master processing core comprises a code protection defined by a protection scheme and wherein the volatile program memory of the slave processing core has a code protection that depends on a setting of the protection scheme.

17. The integrated circuit according to claim 16 , wherein the protection scheme defines a plurality of segments of the non-volatile program memory and wherein each segment has a protection setting in the protection scheme.

18. The integrated circuit according to claim 17 , wherein each protection setting for the non-volatile program memory has a setting for a read operation and a setting for a program or erase operation.

19. The integrated circuit according to claim 17 , wherein the protection scheme provides for a predefined number of security levels, wherein each security level defines a protection setting for each segment.

20. The integrated circuit according to claim 19 , wherein the code protection for the volatile program memory is the same as the code protection for one of the segments of the non-volatile program memory.

21. The integrated circuit according to claim 20 , wherein a register stores which segment of the non-volatile program memory is selected to provide the code protection setting for the volatile program memory.

22. The integrated circuit according to claim 18 , wherein a setting for a read operation of the non-volatile program memory applies to read and write operations of the volatile program memory.

23. The integrated circuit according to claim 17 , wherein when a segment is protected, depending on a protection setting, an instruction executed from one segment may not operate on a different segment.

24. The integrated circuit according to claim 17 , wherein when a segment is protected, depending on a protection setting, a read instruction executed from one segment may operate only on a predefined area of a different segment.

25. The integrated circuit according to claim 24 , wherein the predefined area stores interrupt vectors.

26. The integrated circuit according to claim 17 , wherein the non-volatile program memory comprises a boot segment and a general segment.

27. The integrated circuit according to claim 26 , wherein the non-volatile program memory further comprises a test segment.

28. A method for providing firmware for a processing core in a multi-core integrated circuit processing device comprising a first processing core having a first central processing unit coupled with a non-volatile program memory and a second processing core operating independently from the first processing core and having a second central processing unit coupled with volatile program memory, wherein a program instruction length of program instructions processed by the second processing core is larger than an internal data bus length of the master processing core;
the method comprising:
executing a dedicated instruction within the first central processing unit which causes a program instruction for the slave processing core to be written into the non-volatile program memory of the slave processing core.

29. The method according to claim 28 , wherein the dedicated instruction has a first operand defining a source address and a second operand defining a destination address, wherein the destination address is auto-incremented after execution of the dedicated instruction.

30. The method according to claim 28 , wherein u

Assignees

• Microchip Tech Inc

Inventors

• Catherwood Michael
• Mickey David
• Kris Bryan
• Wilkie Calum
• Sachs Jason
• Reiter Andreas

Classifications

• G06F13/4068

  Electrical coupling · CPC title

• G06F12/14

  Protection against unauthorised use of memory {or access to memory} · CPC title

• G06F9/3877 Primary

  using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12) · CPC title

• G06F13/1673 Primary

  using buffers · CPC title

• G06F9/3879

  for non-native instruction execution, e.g. executing a command; for Java instruction set · CPC title