Co-operative memory management system

US10776260B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-10776260-B1
Application numberUS-201916412668-A
CountryUS
Kind codeB1
Filing dateMay 15, 2019
Priority dateMay 15, 2019
Publication dateSep 15, 2020
Grant dateSep 15, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A system for memory management that comprises: a computing system having a finite amount of memory and a physical computer readable storage memory readable by a processing circuit and storing instructions for execution by the circuit to: set, by a memory coordinator, the urgency of each memory consumer; adjust, by the memory coordinator, the memory quota of each memory consumer—such that the sum of the memory quota of each memory consumer does not exceed the memory; and adjust, by each memory consumer, its memory usage in response to a quota input and an urgency input from the memory coordinator to the memory consumer. The memory is managed by a memory coordinator and memory consumers; and consumed by the memory consumers. Each memory consumer has: a memory quota, an urgency and a memory usage. Also, the urgency of each memory consumer increases as the sum of the memory usage of the plurality of memory consumers approaches the finite amount of memory.

First claim

Opening claim text (preview).

What is claimed is: 1. A system for memory management, the system comprising: a computing system having a finite amount of memory, wherein the finite amount of memory is: managed by a memory coordinator and a plurality of memory consumers; and consumed by the plurality of memory consumers, each memory consumer having a memory quota, an urgency and a memory usage; and a physical computer readable storage memory readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method, the method comprising: setting, by the memory coordinator, the urgency of each memory consumer; adjusting, by the memory coordinator, the memory quota of each memory consumer wherein a sum of the memory quota of each memory consumer does not exceed the finite amount of memory; and adjusting, by each memory consumer, its memory usage in response to a quota input and an urgency input from the memory coordinator to the memory consumer; wherein the urgency of each memory consumer increases as the sum of the memory usage of the plurality of memory consumers approaches the finite amount of memory. 2. The system of claim 1 , wherein the method further comprises: setting, by the memory coordinator, a first memory limit that is a fraction of the finite amount of memory, wherein a sum of the memory quotas is less than the first memory limit. 3. The system of claim 2 , wherein the first memory limit is 80%-95% of the finite amount of memory. 4. The system of claim 2 , wherein the method further comprises: setting, by the memory coordinator, a second memory limit that is a fraction of the first memory limit, wherein the sum of the quotas is less than the second memory limit. 5. The system of claim 4 , wherein the second memory limit is 85%-90% of the first memory limit. 6. The system of claim 1 , wherein the method further comprises releasing, by the memory consumer, an amount of memory held by the memory consumer as the memory usage of the memory consumer approaches or exceeds the memory quota of the memory consumer. 7. The system of claim 6 , wherein the amount of memory released by the memory consumer depends on the urgency input from the memory coordinator. 8. The system of claim 1 , wherein adjusting the memory quota of each memory consumer further comprises: requesting, by the memory coordinator, the memory usage of each consumer; ranking, by the memory coordinator, each memory consumer based on a quota need and a memory release capability of each memory consumer; and rebalancing, by the memory coordinator, the quota of each memory consumer. 9. The system of claim 8 , wherein the memory release capability is based, in part, on: a) a difference between the memory usage and the quota; b) rate of change of the difference over time; and c) rate of change in the memory usage over time. 10. The system of claim 1 , wherein the method further comprises releasing, by the memory consumer, an amount of memory held by the memory consumer without the quota input or the urgency input from the memory coordinator. 11. A computer program product for memory management comprising: a computing system having a finite amount of memory, wherein the finite amount of memory is: managed by a memory coordinator and a plurality of memory consumers; and consumed by the plurality of memory consumers, each memory consumer having a memory quota, an urgency and a memory usage; and a physical computer readable storage memory readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising: setting, by the memory coordinator, the urgency of each memory consumer; balancing, by the memory coordinator, the memory quota of each memory consumer wherein a sum of the memory usage of each memory consumer does not exceed the finite amount of memory; and adjusting, by each memory consumer, the memory usage of the memory consumer in response to a quota input and an urgency input from the memory coordinator to the memory consumer; wherein the urgency of each memory consumer increases as the sum of the memory usage of each memory consumer approaches the finite amount of memory. 12. The computer program product of claim 11 , wherein the method further comprises: setting, by the memory coordinator, a first memory limit that is a fraction of the finite amount of memory, wherein a sum of the memory quotas is less than the first memory limit. 13. The computer program product of claim 12 , wherein the first memory limit is 80%-95% of the finite amount of memory. 14. The computer program product of claim 12 , wherein the method further comprises: setting, by the memory coordinator, a second memory limit that is a fraction of the first memory limit, wherein the sum of the quotas is less than the second memory limit. 15. The computer program product of claim 14 , wherein the second memory limit is 85%-90% of the first memory limit. 16. The computer program product of claim 11 , wherein the method further comprises releasing, by the memory consumer, an amount of memory held by the memory consumer as the memory usage of the memory consumer approaches or exceeds the memory quota of the memory consumer. 17. The computer program product of claim 16 , wherein the memory released by the memory consumer depends on the urgency input from the memory coordinator. 18. The computer program product of claim 11 , wherein balancing the memory quota of each memory consumer further comprises: requesting, by the memory coordinator, the memory usage of each consumer; ranking, by the memory coordinator, each memory consumer based on a quota need and a memory release capability of each memory consumer; and rebalancing, by the memory coordinator, the quota of each memory consumer. 19. The computer program product of claim 18 , wherein the a memory release capability depends partly on: a) a difference between the memory usage and the quota; b) rate of change of the difference over time; and c) rate of change in the memory usage over time. 20. The computer program product of claim 11 , wherein the method further comprises releasing, by the memory consumer, an amount of memory held by the memory consumer, without the quota input or the urgency input from the memory coordinator.

Assignees

Inventors

Classifications

  • Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

  • Mechanisms to release resources · CPC title

  • Resource capping · CPC title

  • G06F9/5016Primary

    the resource being the memory · CPC title

  • Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory · CPC title

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What does patent US10776260B1 cover?
A system for memory management that comprises: a computing system having a finite amount of memory and a physical computer readable storage memory readable by a processing circuit and storing instructions for execution by the circuit to: set, by a memory coordinator, the urgency of each memory consumer; adjust, by the memory coordinator, the memory quota of each memory consumer—such that the su…
Who is the assignee on this patent?
Kinaxis Inc
What technology area does this patent fall under?
Primary CPC classification G06F9/5016. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Sep 15 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).