Memory store error check

Patent metadata

Field	Value
Publication number	US-10776192-B2
Application number	US-201515756956-A
Country	US
Kind code	B2
Filing date	Sep 17, 2015
Priority date	Sep 17, 2015
Publication date	Sep 15, 2020
Grant date	Sep 15, 2020

Abstract

Techniques for memory store error checks are provided. In one aspect, a process running on a processor may execute an instruction to store a first value in memory. The processor may store a plurality of values, including the first value, from a plurality of processes to the memory. A check on a synchronous error notification path may be performed to determine whether an error in storing at least one of the plurality of values occurred.

First claim

We claim:

1. A method comprising:
initiating execution of a first process by a processor, wherein the first process causes a memory controller to store a first value associated with the first process in a memory;
upon initiating the execution of the first process, triggering a synchronous error check process and an asynchronous error check process, wherein the synchronous error check process comprises:
proactively accessing an error counter to determine a current value;
determining that the first value was written to the memory;
proactively accessing the error counter to determine an updated value; and
when the current value and the updated value are different, indicating that a first error occurred in writing to the memory; and

wherein the asynchronous error check process comprises:
waiting for an operating system signal to identify whether the memory controller successfully stored the first value associated with the first process in the memory or a second error occurred; and
when the operating system signal identifies that the memory controller did not successfully store the first value associated with the first process in the memory and the second error occurred, determining that incrementing the error counter during the synchronous error check process was caused by the first process.

2. The method of claim 1 , wherein the operating system signal is an interrupt signal.

3. The method of claim 1 , further comprising:
initiating a corrective action in response to the identification that the memory controller did not successfully store the first value associated with the first process in the memory and the second error occurred.

4. The method of claim 3 , wherein the corrective action includes initiating a second execution of the first process.

5. The method of claim 3 , wherein the corrective action includes mirroring data between two sections of the memory.

6. The method of claim 3 , wherein the corrective action includes transmitting a notification that the first error was caused by the first process.

7. The method of claim 1 , wherein the memory controller is configured to increment the error counter when the first error occurs in writing to the memory.

8. The method of claim 1 , wherein when the first error occurred and the second error occurred, the method further comprises determining that a Dual In-Line Memory Module (DIMM) failed.

9. A non-transitory processor readable medium containing a set of instructions which, when executed by a processor, cause the processor to:
initiate execution of a first process by a processor, wherein the first process causes a memory controller to store a first value associated with the first process in a memory;
upon initiating the execution of the first process, trigger a synchronous error check process and an asynchronous error check process, wherein the synchronous error check process comprises:
proactively accessing an error counter to determine a current value;
determining that the first value was written to the memory;
proactively accessing the error counter to determine an updated value; and
when the current value and the updated value are different, indicating that a first error occurred in writing to the memory; and

wherein the asynchronous error check process comprises:
waiting for an operating system signal to identify whether the memory controller successfully stored the first value associated with the first process in the memory or a second error occurred; and
when the operating system signal identifies that the memory controller did not successfully store the first value associated with the first process in the memory and the second error occurred, determining that incrementing the error counter during the synchronous error check process was caused by the first process.

10. The non-transitory processor readable medium of claim 9 , wherein the processor is further configured:
map the error counter to an address space of the first process.

11. The non-transitory processor readable medium of claim 9 , wherein the processor is further configured to:
obtain details related to the first error.

12. The non-transitory processor readable medium of claim 11 , wherein the obtained details related to the first error include a physical address in the memory and the processor is further configured to:
determine a process whose virtual address space maps to the physical address; and
transmit a notification to the process.

13. The medium of claim 11 wherein the obtained details related to the first error include:
an indication of a failed memory device.

14. The medium of claim 11 wherein the obtained details related to the first error include:
a range of addresses in which the first error occurred.

15. A system comprising:
a memory;
a memory controller to provide an error counter, the error counter changing when an error occurs in writing a value to the memory; and
a processor to execute instructions to:
initiate execution of a first process, wherein the first process causes the memory controller to store a first value associated with the first process in the memory;
upon initiating the execution of the first process, trigger a synchronous error check process and an asynchronous error check process, wherein the synchronous error check process comprises:
proactively accessing the error counter to determine a current value;
determining that the first value was written to the memory;
proactively accessing the error counter to determine an updated value; and
when the current value and the updated value are different, indicating that a first error occurred in writing to the memory; and

wherein the asynchronous error check process comprises:
waiting for an operating system signal to identify whether the memory controller successfully stored the first value associated with the first process in the memory or a second error occurred; and
when the operating system signal identifies that the memory controller did not successfully store the first value associated with the first process in the memory and the second error occurred, determining that incrementing the error counter during the synchronous error check process was caused by the first process.

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Lillibridge Mark
• Byrne John L

Classifications

• G06F11/073 Primary

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

• G06F11/0784

  Routing of error reports, e.g. with a specific transmission path or data flow · CPC title

• G06F12/10

  Address translation · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G11C29/022

  in I/O circuitry · CPC title