Method and apparatus for controlling power consumption of an integrated circuit

Patent metadata

Field	Value
Publication number	US-10775876-B2
Application number	US-201715858138-A
Country	US
Kind code	B2
Filing date	Dec 29, 2017
Priority date	Dec 29, 2017
Publication date	Sep 15, 2020
Grant date	Sep 15, 2020

Abstract

A method and apparatus control power consumption of at least one functional unit on an integrated circuit by determining that a change in a first performance state is required for the at least one functional unit, and changing the first performance state to a second performance state that sets voltage for the functional unit to be at an under-voltage margin setting with respect to a nominal product minimum voltage of the functional unit.

First claim

The invention claimed is:

1. A method of controlling power consumption of at least one functional unit on an integrated circuit, the method comprising:
determining, by logic circuitry, that a change in a first performance state is required for the at least one functional unit based on aggregated activity data of the at least one functional unit; and
changing, by the logic circuitry, the first performance state to a second performance state that sets voltage for the at least one functional unit to be at an under-voltage margin setting with respect to a nominal product minimum voltage of the at least one functional unit such that a voltage level of the at least one functional unit goes below the nominal product minimum voltage.

2. The method of claim 1 , wherein determining that the change in the first performance state is required for the at least one functional unit includes accruing activity data representing an amount of time that the at least one functional unit has operated at a non-low power setting, and wherein the method includes restricting operation of the at least one functional unit from the non-low power setting.

3. The method of claim 2 , wherein the activity data comprises at least one of: performance state data, operating voltage data, temperature data, electric current data, and margin profile state data of the at least one functional unit.

4. The method of claim 2 , wherein determining that the change in the first performance state is required for the at least one functional unit further comprises:
aggregating, by the logic circuitry, the activity data of the at least one functional unit to calculate the aggregated activity data;
comparing, by the logic circuitry, the aggregated activity data to a threshold level of the at least one functional unit, wherein:
when the aggregated activity data is beyond the threshold level, the logic circuitry restricts operation of the at least one functional unit from the non-low power setting.

5. The method of claim 4 , wherein:
changing the first performance state to the second performance state comprises selecting, by the logic circuitry, corresponding performance margin profile state data of the at least one functional unit based on the aggregated activity data, and
the performance margin profile state data instructs the logic circuitry to enter a low power mode for the at least one functional unit when the aggregated activity data indicates that the at least one functional unit has been operating at the non-low power setting for a predetermined period of time.

6. The method of claim 2 , wherein the integrated circuit comprises a plurality of different types of functional units and each of the different types of functional units has a different corresponding under-voltage margin setting and over-voltage margin setting.

7. The method of claim 6 , further comprising:
accessing, by the logic circuitry, corresponding performance margin profile state data for at least one of the plurality of functional units,
wherein each of the corresponding performance margin profile state data comprises a plurality of performance states for a corresponding functional unit;
wherein at least one of the performance states sets the voltage for the corresponding functional unit to be at the under-voltage margin setting of the corresponding functional unit; and
wherein changing the first performance state to the second performance state comprises selecting and using at least one of the corresponding performance margin profile state data based on the aggregated activity data of the corresponding functional unit.

8. The method of claim 7 , further comprising storing, by memory, the performance margin profile state data corresponding to each of the different functional units.

9. The method of claim 8 , further comprising storing, by memory, data regarding the change in the first performance state of the plurality of functional units for accessing by the logic circuitry.

10. The method of claim 1 , wherein the functional unit is SRAM.

11. The method of claim 1 , wherein the logic circuitry comprises dynamic voltage and frequency scaling (DVFS) logic circuitry that selects the second performance state to include a change in a frequency of operation for the at least one functional unit.

12. An integrated circuit, comprising:
at least one functional unit;
a power management circuit, operatively coupled to the at least one functional unit, operative to:
control power consumption of the at least one functional unit by determining that a change in a first performance state is required for the at least one functional unit based on aggregated activity data of the at least one functional unit; and
change the first performance state to a second performance state that sets voltage for the at least one functional unit to be at an under-voltage margin setting with respect to a nominal product minimum voltage of the at least one functional unit such that a voltage level of the at least one functional unit goes below the nominal product minimum voltage.

13. The integrated circuit of claim 12 , wherein the power management circuit determines that the change in the first performance state is required for the at least one functional unit by accruing activity data representing an amount of time that the at least one functional unit has operated at a non-low power setting, and wherein the power management circuit restricts operation of the at least one functional unit from the non-low power setting.

14. The integrated circuit of claim 13 , wherein the activity data comprises at least one of: performance state data, operating voltage data, temperature data, electric current data, and margin profile state data of the at least one functional unit.

15. The integrated circuit of claim 13 , wherein the power management circuit further comprises state arbiter control logic circuitry operative to:
aggregate the activity data of the at least one functional unit to calculate the aggregated activity data;
compare the aggregated activity data to a threshold level of the at least one functional unit; and
when the aggregated activity data is beyond the threshold level, restrict operation of the at least one functional unit from the non-low power setting.

16. The integrated circuit of claim 15 , wherein the state arbiter control logic circuitry is further operative to select performance margin profile state data corresponding to the at least one functional unit based on the aggregated activity data, and the performance margin profile state data instructs the state arbiter control logic circuitry to enter a low power mode for the at least one functional unit when the aggregated activity data indicates that the at least one functional unit has been operating at the non-low power setting for a predetermined period of time.

17. The integrated circuit of claim 13 , further comprising a plurality of different types of functional units, wherein each of the different types of functional units has a different corresponding under-voltage margin setting and over-voltage margin setting.

18. The integrated circuit of claim 17 , wherein:
the power management circuit further comprises state arbiter control logic circuitry operative to access corresponding performance margin profile state data for the at least one of the plurality of functional units, the performance margin profile state data comprises a plurality of performance states,
at least one of the performance states sets the voltage for the corresponding functional unit to be at the under-voltage margin s

Assignees

• Advanced Micro Devices Inc

Inventors

• Gibney Thomas J
• Arora Sonu

Classifications

• G06F1/324

  by lowering clock frequency · CPC title

• G06F1/3296 Primary

  by lowering the supply or operating voltage · CPC title

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/28

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title