Techniques for marking a substrate using a physical vapor deposition material

US10773494B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10773494-B2
Application numberUS-201715812058-A
CountryUS
Kind codeB2
Filing dateNov 14, 2017
Priority dateAug 25, 2009
Publication dateSep 15, 2020
Grant dateSep 15, 2020

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Techniques, processes and structures are disclosed for providing markings on products, such as electronic devices. For example, the markings can be formed using physical vapor deposition (PVD) processes to deposit a layer of material. The markings or labels may be textual and/or graphic. The markings are deposited on a compliant layer that is disposed on a surface to be marked. The compliant layer is arranged to isolate the surface to be marked from the layer of material deposited using the PVD process.

First claim

Opening claim text (preview).

What is claimed is: 1. An electronic device comprising: a glass housing layer having opposing exterior and interior surfaces; a buffer layer on the interior surface of the glass housing layer that includes silicon dioxide; and a physical vapor deposition layer deposited on the buffer layer. 2. The electronic device defined in claim 1 wherein the physical vapor deposition layer is viewable through the exterior surface of the glass housing. 3. The electronic device defined in claim 2 wherein the physical vapor deposition layer forms a logo. 4. The electronic device defined in claim 2 wherein the physical vapor deposition layer forms text. 5. The electronic device defined in claim 1 wherein the buffer layer has a thickness between 50 nm and 500 nm. 6. The electronic device defined in claim 1 wherein the buffer layer isolates the interior surface of the glass housing layer from the physical vapor deposition layer. 7. The electronic device defined in claim 1 further comprising a layer of ink formed over the silicon dioxide of the buffer layer. 8. The electronic device defined in claim 1 wherein the buffer layer is transparent. 9. The electronic device defined in claim 1 further comprising: an additional housing layer; and sidewalls extending between the glass housing layer and the additional housing layer, wherein the buffer layer and the physical vapor deposition layer are interposed between the glass housing layer, the additional housing layer, and the sidewalls. 10. The electronic device defined in claim 1 wherein the buffer layer includes polyvinyl acetate. 11. An electronic device comprising: a glass housing layer having opposing interior and exterior surfaces; a buffer layer on the interior surface of the glass housing; and a physical vapor deposition coating deposited on the buffer layer, wherein the physical vapor deposition layer is viewable through the exterior surface of the glass housing and the buffer layer. 12. The electronic device defined in claim 11 wherein the buffer layer includes silicon dioxide. 13. The electronic device defined in claim 11 wherein the buffer layer comprises polyvinyl acetate. 14. The electronic device defined in claim 11 further comprising: a housing having an interior and an exterior, wherein the glass housing layer is mounted in the housing with the buffer layer and the physical vapor deposition layer in the interior of the housing. 15. The electronic device defined in claim 14 wherein the buffer layer has a first thickness, the physical vapor deposition has a second thickness, and the first thickness is greater than the first thickness. 16. An electronic device comprising: a glass housing layer having opposing interior and exterior surfaces; a buffer layer on the interior surface of the glass housing layer, wherein the buffer layer comprises silicon dioxide; and a physical vapor deposition coating deposited on the buffer layer, wherein the physical vapor deposition layer comprises reflective structures. 17. The electronic device defined in claim 16 wherein the physical vapor deposition coating is viewable through the exterior surface of the glass housing. 18. The electronic device defined in claim 17 wherein the buffer layer has a thickness between 50 nm and 500 nm. 19. The electronic device defined in claim 18 wherein the physical vapor coating has a thickness between 25 nm and 250 nm. 20. The electronic device defined in claim 17 wherein the buffer layer has a thickness between 1 micron and 10 microns.

Assignees

Inventors

Classifications

  • B05D5/06Primary

    to obtain multicolour or other optical effects (B05D5/02 takes precedence) · CPC title

  • one layer at least containing silicon, hydrogenated silicon or a silicide · CPC title

  • using masks · CPC title

  • Deposition of sublayers, e.g. to promote adhesion of the coating (C23C14/027 takes precedence) · CPC title

  • Next to addition polymer from unsaturated monomers · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10773494B2 cover?
Techniques, processes and structures are disclosed for providing markings on products, such as electronic devices. For example, the markings can be formed using physical vapor deposition (PVD) processes to deposit a layer of material. The markings or labels may be textual and/or graphic. The markings are deposited on a compliant layer that is disposed on a surface to be marked. The compliant la…
Who is the assignee on this patent?
Apple Inc
What technology area does this patent fall under?
Primary CPC classification B05D5/06. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Sep 15 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).