Method for manufacturing phase change memory

Patent metadata

Field	Value
Publication number	US-10770656-B2
Application number	US-201816136464-A
Country	US
Kind code	B2
Filing date	Sep 20, 2018
Priority date	Sep 20, 2018
Publication date	Sep 8, 2020
Grant date	Sep 8, 2020

Abstract

Method(s) and apparatuses for forming a phase change memory. A method includes: forming a crystalline phase-change layer at a first position in along a surface of a first semiconductor layer, and forming an amorphous phase-change layer at a second position along the surface of a second semiconductor layer, wherein the crystalline phase-change layer and the amorphous phase-change layer are in contact.

First claim

What is claimed is:

1. A method for manufacturing a phase-change memory the method comprising:
forming a crystalline phase-change layer at a first position within a recess of an insulation layer; and
forming an amorphous phase-change layer at second position which differs from the first position within the recess; and
forming a recess liner layer that bounds side and bottom portions of the recess.

2. The method according to claim 1 , wherein forming the amorphous phase-change layer is performed after forming the crystalline phase-change layer.

3. The method according to claim 1 , wherein forming the crystalline phase-change layer is performed after forming the amorphous phase-change layer.

4. The method according to claim 3 , wherein
forming the amorphous phase-change layer includes forming a first amorphous phase-change layer, and
the method further comprises forming a second amorphous phase-change layer at a third position in the recess after forming the crystalline phase-change layer, wherein the third position differs from the first position and the second position.

5. The method according to claim 1 , wherein
forming the crystalline phase-change layer and forming the amorphous phase-change layer fills a cavity defined by the recess with the crystalline phase-change layer and the amorphous phase-change layer, and
the amorphous phase-change layer and the crystalline phase-change layer are formed in the cavity of the recess so that the amorphous phase-change layer has a smaller volume than the crystalline phase-change layer.

6. The method according to claim 1 , wherein forming the crystalline phase-change layer comprises:
forming the crystalline phase-change layer with a different material composition than the amorphous phase-change layer but includes elements that are also included in the amorphous phase-change layer.

7. The method according to claim 1 , wherein the insulation layer is set to have a higher temperature when the crystalline phase-change layer is formed than when the amorphous phase-change layer is formed.

8. A method comprising:
forming a crystalline phase-change layer at a first position within a recess along a surface of a first semiconductor layer;
forming an amorphous phase-change layer at a second position within the recess, wherein the crystalline phase-change layer and the amorphous phase-change layer contact; and
forming a recess liner layer that bounds side and bottom portions of the recess.

9. The method according to claim 8 further comprising:
forming a single polycrystalline phase-change layer from the amorphous phase-change layer and the the crystalline phase-change layer.

10. The method according to claim 9 further comprising:
forming a first electrode and a second electrode in contact with the single polycrstalline phase-change layer.

11. The method according to claim 8 , wherein forming the crystalline phase-change layer is performed after forming the amorphous phase-change layer.

12. The method according to claim 11 further comprising:
forming a liner in contact with the crystalline phase-change layer without contacting the amorphous-change layer; and
forming a first electrode in contact with the liner.

13. The method according to claim 12 further comprising:
forming a single polycrystalline phase-change layer from the amorphous phase-change layer and the the crystalline phase-change layer, wherein the single polycrstalline phase-change layer is in contact with the liner.

14. The method according to claim 13 , wherein forming the single polycrystalline phase-change layer from the amorphous phase-change layer and the the crystalline phase-change layer comprises:
heating the amorphous phase-change layer and the crystalline phase-change layer to a crystalline temperature or higher.

15. The method according to claim 14 further comprising:
forming a second electrode over the single polycrstalline phase-change layer.

16. The method according to claim 12 , wherein the single polycrstalline phase-change layer is between ninety-three percent to ninety-seven percent void free.

17. The method according to claim 12 , wherein the single polycrstalline phase-change layer is approximately ninety-seven percent void free.

18. The method according to claim 12 , wherein the single polycrstalline phase-change layer is a germanium antimony telluride (Ge x Sb y Te z :GST) layer.

Assignees

• IBM
• Ulvac Tech Inc

Inventors

• Fraczak Gloria Wing Yun
• Brightsky Matthew
• Lam Chung Hon
• Carta Fabio
• Bruce Robert
• Masuda Takeshi
• Suu Koukou

Classifications

• H01L45/1286

  Electricity · mapped topic

• H01L45/1253

  Electricity · mapped topic

• H01L45/144 Primary

  Electricity · mapped topic

• H01L45/06

  Electricity · mapped topic

• H01L45/1683

  Electricity · mapped topic